Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
655c5444
Commit
655c5444
authored
Aug 27, 2012
by
Walter Lee
Committed by
Walter Lee
Aug 27, 2012
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Fix doc typo.
* doc/md.texi (TILE-Gx): Fix typo. From-SVN: r190729
parent
15a611c0
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
6 additions
and
2 deletions
+6
-2
gcc/ChangeLog
+4
-0
gcc/doc/md.texi
+2
-2
No files found.
gcc/ChangeLog
View file @
655c5444
2012-08-27 Walter Lee <walt@tilera.com>
2012-08-27 Walter Lee <walt@tilera.com>
* doc/md.texi (TILE-Gx): Fix typo.
2012-08-27 Walter Lee <walt@tilera.com>
* config/tilegx/tilegx.c (tilegx_function_profiler): Fix typo.
* config/tilegx/tilegx.c (tilegx_function_profiler): Fix typo.
config/tilepro/tilepro.c (tilepro_function_profiler): Ditto.
config/tilepro/tilepro.c (tilepro_function_profiler): Ditto.
...
...
gcc/doc/md.texi
View file @
655c5444
...
@@ -3580,7 +3580,7 @@ Register B14 (aka DP).
...
@@ -3580,7 +3580,7 @@ Register B14 (aka DP).
@
itemx
R07
@
itemx
R07
@
itemx
R08
@
itemx
R08
@
itemx
R09
@
itemx
R09
@
itemx
R
0
10
@
itemx
R10
Each
of
these
represents
a
register
constraint
for
an
individual
Each
of
these
represents
a
register
constraint
for
an
individual
register
,
from
r0
to
r10
.
register
,
from
r0
to
r10
.
...
@@ -3658,7 +3658,7 @@ The integer constant 0xffffffff00000000.
...
@@ -3658,7 +3658,7 @@ The integer constant 0xffffffff00000000.
@
itemx
R07
@
itemx
R07
@
itemx
R08
@
itemx
R08
@
itemx
R09
@
itemx
R09
@
itemx
R
0
10
@
itemx
R10
Each
of
these
represents
a
register
constraint
for
an
individual
Each
of
these
represents
a
register
constraint
for
an
individual
register
,
from
r0
to
r10
.
register
,
from
r0
to
r10
.
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment