Commit 65239d20 by Richard Sandiford Committed by Richard Sandiford

mips-protos.h (mips_regno_mode_ok_for_base_p): Give the STRICT_P argument type…

mips-protos.h (mips_regno_mode_ok_for_base_p): Give the STRICT_P argument type "bool" rather than "int".

gcc/
	* config/mips/mips-protos.h (mips_regno_mode_ok_for_base_p): Give
	the STRICT_P argument type "bool" rather than "int".
	(mips_legitimate_address_p): Likewise.
	(fp_register_operand, lo_operand): Delete.
	(mips_subword): Give the HIGH_P argument type "bool" rather than "int".
	(mips_emit_scc): Rename to...
	(mips_expand_scc): ...this.
	(gen_conditional_branch): Rename to...
	(mips_expand_conditional_branch): ...this.
	(gen_conditional_move): Rename to...
	(mips_expand_conditional_move): ...this.
	(mips_gen_conditional_trap): Rename to...
	(mips_expand_conditional_trap): ...this and take an rtx code instead
	of an operands array.
	(mips_expand_call): Give the SIBCALL_P argument type "bool"
	rather than "int".
	(mips_emit_fcc_reload): Rename to...
	(mips_expand_fcc_reload): ...this.
	(init_cumulative_args): Rename to...
	(mips_init_cumulative_args): ...this and remove the libname argument.
	(function_arg_advance): Rename to...
	(mips_function_arg_advance): ...this.
	(function_arg): Rename to...
	(mips_function_arg): ...this and use "rtx" instead of
	"struct rtx_def *".
	(function_arg_boundary): Rename to...
	(mips_function_arg_boundary): ...this.
	(mips_expand_unaligned_load): Rename to...
	(mips_expand_ext_as_unaligned_load): ...this and give the WIDTH
	and BITPOS arguments type "HOST_WIDE_INT".
	(mips_expand_unaligned_store): Rename to...
	(mips_expand_ins_as_unaligned_store): ...this and give the WIDTH
	and BITPOS arguments type "HOST_WIDE_INT".
	(override_options): Rename to...
	(mips_override_options): ...this.
	(print_operand): Rename to...
	(mips_print_operand): ...this.
	(print_operand_address): Rename to...
	(mips_print_operand_address): ...this.
	(mips_output_ascii): Remove the PREFIX argument.
	(mips_expand_epilogue): Give the SIBCALL_P argument type "bool"
	rather than "int".
	(mips_can_use_return_insn): Return a "bool" rather than an "int".
	(mips_function_value): Remove the FUNC argument.  Use "rtx" instead
	of "struct rtx_def *".
	(mips_secondary_reload_class): Give the IN_P argument type "bool"
	rather than "int".
	(build_mips16_call_stub): Delete.
	(mips_store_data_bypass_p): Return a "bool" rather than an "int".
	(mips_use_ins_ext_p): Give the second and third arguments type
	"HOST_WIDE_INT" rather than "rtx".
	* config/mips/mips.h: Update after the above changes.  Tweak comments
	and formatting.
	(SECONDARY_INPUT_RELOAD_CLASS): Pass a boolean IN_P argument.
	(SECONDARY_OUTPUT_RELOAD_CLASS): Likewise.
	(mips_print_operand_punct, mips_hard_regno_mode_ok): Change the
	element type from "char" to "bool".
	(mips_section_threshold, sym_lineno, set_noat, mips_branch_likely)
	(mips_cpu_info_table): Delete.
	* config/mips/mips.md: Update after the above changes.  Tweak some
	formatting.
	* config/mips/mips-ps-3d.md: Likewise.
	* config/mips/mips.c: Tweak comments and formatting.
	Use NULL-like macros rather than 0 in various places.
	(mips_section_threshold): Rename to...
	(mips_small_data_threshold): ...this and give it an unsigned type.
	(num_source_filenames): Remove explicit initialization.
	(sdb_label_count): Likewise.
	(sym_lineno): Delete.
	(set_noat): Make static.
	(mips_branch_likely): Likewise, and give it type "bool".
	(mips_isa_info): Rename to...
	(mips_isa_option_info): ...this.
	(mips_flag_delayed_branch): Rename to...
	(mips_base_delayed_branch): ...this.
	(mips_split_addresses): Delete.
	(mips_print_operand_punct, mips_hard_regno_mode_ok): Change the
	element type from "char" to "bool".
	(mips_regno_to_class): Add an explicit array size.
	(mips16_flipper): Change from type "int" to type "bool".
	(mips_comp_type_attributes): Remove redundant FUNCTION_TYPE check.
	(mips_tls_operand_p): Rename to...
	(mips_tls_symbol_p): ...this.
	(mips_global_symbol_p): Remove redundant "const".
	(mips_offset_within_alignment_p): Simplify.
	(mips_regno_mode_ok_for_base_p): Change the name of the last argument
	to STRICT_P and give it type bool.
	(mips_valid_base_register_p): Likewise.
	(mips_classify_address): Likewise.
	(mips_legitimate_address_p): Likewise.
	(mips16_unextended_reference_p): Take the offset as an
	"unsigned HOST_WIDE_INT" rather than an "rtx".  Simplify.
	(mips_const_insns): Use IN_RANGE.
	(mips_force_temporary): Remove an unnecessary copy_rtx.
	(mips16_gp_pseudo_reg): Simplify.
	(mips_split_symbol): Remove an unnecessary copy_rtx.
	(mips_legitimize_tls_address): Only create registers if we need them.
	(mips_legitimize_address): Use mips_split_plus.
	(mips_move_integer): Swap DEST and TEMP arguments.  Rename local
	variable COST to NUM_OPS.
	(mips_legitimize_move): Use gen_lowpart.
	(mips_rewrite_small_data): Rename the OP parameter to PATTERN.
	(m16_check_op): Use IN_RANGE.
	(mips_subword): Give the HIGH_P argument type "bool" rather than "int".
	(mips_split_doubleword_move): Pass booleans to mips_subword.
	(mips_output_move): Store the mode in a local variable.
	Explicitly assert that this function does not deal with
	MFLO and MFHI.  Use SMALL_OPERAND_UNSIGNED.  Make order of
	cases more consistent.
	(mips_relational_operand_ok_p): Rename to...
	(mips_int_order_operand_ok_p): ...this.
	(mips_canonicalize_comparison): Rename to...
	(mips_canonicalize_int_order_test): ...this.
	(mips_emit_int_relational): Rename to...
	(mips_emit_int_order_test): ...this.  Store the mode in a local
	variable.
	(mips_reverse_fp_cond_p): Rename to...
	(mips_reversed_fp_cond): ...this.
	(mips_emit_compare): Make the order of the statements more consistent.
	(mips_emit_scc): Rename to...
	(mips_expand_scc): ...this.
	(gen_conditional_branch): Rename to...
	(mips_expand_conditional_branch): ...this.
	(gen_conditional_move): Rename to...
	(mips_expand_conditional_move): ...this.  Build the condition
	separately from the main pattern.
	(mips_gen_conditional_trap): Rename to...
	(mips_expand_conditional_trap): ...this and take an rtx code instead
	of an operands array.  Simplify.
	(init_cumulative_args): Rename to...
	(mips_init_cumulative_args): ...this.  Use memset rather than a
	copy from a zeroed static.  Use prototype_p and stdarg_p.
	(mips_arg_info): Rename to...
	(mips_get_arg_info): ...this and put the INFO argument first.
	(function_arg): Rename to...
	(mips_function_arg): ...this and use "rtx" instead of
	"struct rtx_def *".  Only split structures into chunks if 
	TARGET_HARD_FLOAT, rather than checking !TARGET_SOFT_FLOAT on
	a chunk-by-chunk basis.  Use SCALAR_FLOAT_TYPE_P instead of a
	comparison with REAL_TYPE.  Rename local variable REG to REGNO
	and make it unsigned.
	(function_arg_advance): Rename to...
	(mips_function_arg_advance): ...this.
	(function_arg_boundary): Rename to...
	(mips_function_arg_boundary): ...this.
	(mips_pad_arg_upward): Use SCALAR_INT_MODE_P instead of a comparison
	with MODE_INT.
	(mips_fpr_return_fields): Use SCALAR_FLOAT_TYPE_P instead of a
	comparison with REAL_TYPE.
	(mips_function_value): Remove the FUNC argument.  Rename local
	variable UNSIGNEDP to UNSIGNED_P.
	(mips_return_in_memory): Use IN_RANGE.
	(mips_setup_incoming_varargs): Pass a boolean rather than an int
	to FUNCTION_ARG_ADVANCE.
	(mips_gimplify_va_arg_expr): Rename local variable INDIRECT
	to INDIRECT_P.  Remove a redundant mips_abi check.  Only calculate
	SIZE and RSIZE if needed.
	(mips16_stub): Rename FPRET to FP_RET_P and give it type "bool"
	rather than "int".
	(build_mips16_function_stub): Rename to...
	(mips16_build_function_stub): ...this.
	(build_mips16_call_stub): Rename to...
	(mips16_build_call_stub): ...this.  Make static, and return a
	"bool" rather than an "int".  Rename the ARG_SIZE argument to
	ARGS_SIZE.  Rename the local variable FPRET to FP_RET_P and give
	it type "bool".  Use "jr" rather than "j".  Use XNEW.  Simplify.
	(mips_load_call_address): Give the SIBCALL_P argument type "bool"
	rather than "int".
	(mips_expand_call): Likewise.  Assert that MIPS16 calls via stubs
	are not sibling ones.
	(mips_emit_fcc_reload): Rename to...
	(mips_expand_fcc_reload): ...this.
	(mips_get_unaligned_mem): Give the WIDTH and BITPOS arguments type
	"HOST_WIDE_INT".
	(mips_expand_unaligned_load): Rename to...
	(mips_expand_ext_as_unaligned_load): ...this and give the WIDTH
	and BITPOS arguments type "HOST_WIDE_INT".  Remove redundant
	SUBREG_BYTE check.
	(mips_expand_unaligned_store): Rename to...
	(mips_expand_ins_as_unaligned_store): ...this and give the WIDTH
	and BITPOS arguments type "HOST_WIDE_INT".
	(mips_use_ins_ext_p): Rename second and third arguments to WIDTH
	and BITPOS and give them type "HOST_WIDE_INT" rather than "rtx".
	Use IN_RANGE.
	(mips_init_split_addresses): Replace with...
	(mips_split_addresses_p): ...this new function.
	(mips_init_relocs): Check mips_split_addresses_p () rather than
	mips_split_addresses.  Always initialize mips_split_p with booleans.
	(print_operand_reloc): Rename to...
	(mips_print_operand_reloc): ...this.  Use a gcc_assert rather than
	a fatal_error.
	(print_operand): Rename to...
	(mips_print_operand): ...this.
	(print_operand_address): Rename to...
	(mips_print_operand_address): ...this.  Use GP_REG_FIRST.
	(mips_in_small_data_p): Simplify.
	(mips_output_ascii): Remove the PREFIX argument and "register"
	keywords.  Use the STRING parameter directly and cast to
	"unsigned char".
	(mips16e_collect_argument_save_p): Use IN_RANGE.
	(mips_function_has_gp_insn): Simplify.
	(mips_set_return_address): Use BITSET_P.
	(mips_restore_gp): Use a separate statement to pick the base
	register.
	(mips_output_function_prologue): Use a local FRAME variable.
	(mips_save_reg): Pass booleans to mips_subword.
	(mips_expand_prologue): Use a local FRAME variable.  Use
	cprestore_size to detect when .cprestore is needed.
	(mips_restore_reg): Use GP_REG_FIRST.
	(mips_expand_epilogue): Give the SIBCALL_P argument type "bool"
	rather than "int".  Use local FRAME and REGNO variables.
	(mips_can_use_return_insn): Return a "bool" rather than an "int".
	(mips_secondary_reload_class): Give the IN_P argument type "bool"
	rather than "int".
	(mips_linked_madd_p): Rename arguments to OUT_INSN and IN_INSN.
	(mips_store_data_bypass_p): Return a "bool" rather than an "int".
	(vr4130_swap_insns_p): Rename local variables to DEP1_P and DEP2_P.
	(mips_74k_agen_init): Assume INSN satisfies USEFUL_INSN_P.
	(mips_variable_issue): Do nothing unless INSN satisfies USEFUL_INSN_P.
	(builtin_description): Rename to...
	(mips_builtin_description): ...this.
	(mips_bdesc): Rename to...
	(mips_ps_bdesc): ...this.
	(sb1_bdesc): Rename to...
	(mips_sb1_bdesc): ...this.
	(dsp_bdesc): Rename to...
	(mips_dsp_bdesc): ...this.
	(dsp_32only_bdesc): Rename to...
	(mips_dsp_32only_bdesc): ...this.
	(bdesc_map): Rename to...
	(mips_bdesc_map): ...this.
	(bdesc_arrays): Rename to...
	(mips_bdesc_arrays): ...this.
	(mips_prepare_builtin_arg): Rename OP to OPNO and ARGNUM to ARGNO.
	Tweak error message.
	(mips_expand_builtin_direct): Rename HAS_TARGET to HAS_TARGET_P.
	Rename local variables I and J to OPNO and ARGNO respectively.
	Assert that the number of arguments is no more than the number of
	input operands.
	(mips_expand_builtin_compare): Use an array of arguments rather
	than an array of operands.  Assert that the number of operands is
	as expected.
	(add_constant): Rename to...
	(mips16_add_constant): ...this.  Use XNEW.
	(dump_constants_1): Rename to...
	(mips16_emit_constants_1): ...this.  Use ALL_SCALAR_FIXED_POINT_MODE_P.
	(dump_constants): Rename to...
	(mips16_emit_constants): ...this.
	(mips_sim_wait_reg, mips_sim_record_set): Use END_REGNO.
	(mips_set_mips16_mode): Don't call mips_init_split_addresses.
	Assign mips16_p to was_mips16_p.
	(mips_parse_cpu): Tweak warning message.
	(override_options): Rename to...
	(mips_override_options): ...this.  Move the mips_cost initialization
	out of the "shared with GAS" block.  Quote option names in error
	messages.
	(mips_conditional_register_usage): Make local variable REGNO unsigned.
	(mips_order_regs_for_local_alloc): Remove register keyword.

From-SVN: r129532
parent b5edaa2c
......@@ -166,15 +166,13 @@ struct mips16e_save_restore_info;
extern bool mips_symbolic_constant_p (rtx, enum mips_symbol_context,
enum mips_symbol_type *);
extern int mips_regno_mode_ok_for_base_p (int, enum machine_mode, int);
extern int mips_regno_mode_ok_for_base_p (int, enum machine_mode, bool);
extern bool mips_legitimate_address_p (enum machine_mode, rtx, bool);
extern bool mips_stack_address_p (rtx, enum machine_mode);
extern int mips_address_insns (rtx, enum machine_mode, bool);
extern int mips_const_insns (rtx);
extern int mips_load_store_insns (rtx, rtx);
extern int mips_idiv_insns (void);
extern int fp_register_operand (rtx, enum machine_mode);
extern int lo_operand (rtx, enum machine_mode);
extern bool mips_legitimate_address_p (enum machine_mode, rtx, int);
extern rtx mips_emit_move (rtx, rtx);
extern bool mips_split_symbol (rtx, rtx, enum machine_mode, rtx *);
extern rtx mips_unspec_address (rtx, enum mips_symbol_type);
......@@ -199,47 +197,49 @@ extern int m16_nuimm8_4 (rtx, enum machine_mode);
extern int m16_simm8_8 (rtx, enum machine_mode);
extern int m16_nsimm8_8 (rtx, enum machine_mode);
extern rtx mips_subword (rtx, int);
extern rtx mips_subword (rtx, bool);
extern bool mips_split_64bit_move_p (rtx, rtx);
extern void mips_split_doubleword_move (rtx, rtx);
extern const char *mips_output_move (rtx, rtx);
extern void mips_restore_gp (void);
#ifdef RTX_CODE
extern bool mips_emit_scc (enum rtx_code, rtx);
extern void gen_conditional_branch (rtx *, enum rtx_code);
extern bool mips_expand_scc (enum rtx_code, rtx);
extern void mips_expand_conditional_branch (rtx *, enum rtx_code);
extern void mips_expand_vcondv2sf (rtx, rtx, rtx, enum rtx_code, rtx, rtx);
extern void mips_expand_conditional_move (rtx *);
extern void mips_expand_conditional_trap (enum rtx_code);
#endif
extern void gen_conditional_move (rtx *);
extern void mips_gen_conditional_trap (rtx *);
extern void mips_expand_call (rtx, rtx, rtx, rtx, int);
extern void mips_emit_fcc_reload (rtx, rtx, rtx);
extern void mips_expand_call (rtx, rtx, rtx, rtx, bool);
extern void mips_expand_fcc_reload (rtx, rtx, rtx);
extern void mips_set_return_address (rtx, rtx);
extern bool mips_expand_block_move (rtx, rtx, rtx);
extern void mips_expand_synci_loop (rtx, rtx);
extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx);
extern void function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
tree, int);
extern struct rtx_def *function_arg (const CUMULATIVE_ARGS *,
enum machine_mode, tree, int);
extern int function_arg_boundary (enum machine_mode, tree);
extern void mips_init_cumulative_args (CUMULATIVE_ARGS *, tree);
extern void mips_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
tree, int);
extern rtx mips_function_arg (const CUMULATIVE_ARGS *,
enum machine_mode, tree, int);
extern int mips_function_arg_boundary (enum machine_mode, tree);
extern bool mips_pad_arg_upward (enum machine_mode, const_tree);
extern bool mips_pad_reg_upward (enum machine_mode, tree);
extern void mips_va_start (tree, rtx);
extern bool mips_expand_unaligned_load (rtx, rtx, unsigned int, int);
extern bool mips_expand_unaligned_store (rtx, rtx, unsigned int, int);
extern bool mips_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT,
HOST_WIDE_INT);
extern bool mips_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT,
HOST_WIDE_INT);
extern bool mips_mem_fits_mode_p (enum machine_mode mode, rtx x);
extern void override_options (void);
extern void mips_override_options (void);
extern void mips_conditional_register_usage (void);
extern void mips_order_regs_for_local_alloc (void);
extern HOST_WIDE_INT mips_debugger_offset (rtx, HOST_WIDE_INT);
extern void print_operand (FILE *, rtx, int);
extern void print_operand_address (FILE *, rtx);
extern void mips_print_operand (FILE *, rtx, int);
extern void mips_print_operand_address (FILE *, rtx);
extern void mips_output_external (FILE *, tree, const char *);
extern void mips_output_filename (FILE *, const char *);
extern void mips_output_ascii (FILE *, const char *, size_t, const char *);
extern void mips_output_ascii (FILE *, const char *, size_t);
extern void mips_output_aligned_decl_common (FILE *, tree, const char *,
unsigned HOST_WIDE_INT,
unsigned int);
......@@ -258,9 +258,9 @@ extern HOST_WIDE_INT mips_initial_elimination_offset (int, int);
extern rtx mips_return_addr (int, rtx);
extern enum mips_loadgp_style mips_current_loadgp_style (void);
extern void mips_expand_prologue (void);
extern void mips_expand_epilogue (int);
extern int mips_can_use_return_insn (void);
extern struct rtx_def *mips_function_value (const_tree, const_tree, enum machine_mode);
extern void mips_expand_epilogue (bool);
extern bool mips_can_use_return_insn (void);
extern rtx mips_function_value (const_tree, enum machine_mode);
extern bool mips_cannot_change_mode_class (enum machine_mode,
enum machine_mode, enum reg_class);
......@@ -269,9 +269,8 @@ extern bool mips_modes_tieable_p (enum machine_mode, enum machine_mode);
extern enum reg_class mips_preferred_reload_class (rtx, enum reg_class);
extern enum reg_class mips_secondary_reload_class (enum reg_class,
enum machine_mode,
rtx, int);
rtx, bool);
extern int mips_class_max_nregs (enum reg_class, enum machine_mode);
extern int build_mips16_call_stub (rtx, rtx, rtx, int);
extern int mips_register_move_cost (enum machine_mode, enum reg_class,
enum reg_class);
......@@ -283,13 +282,13 @@ extern const char *mips_output_order_conditional_branch (rtx, rtx *, bool);
extern const char *mips_output_division (const char *, rtx *);
extern unsigned int mips_hard_regno_nregs (int, enum machine_mode);
extern bool mips_linked_madd_p (rtx, rtx);
extern int mips_store_data_bypass_p (rtx, rtx);
extern bool mips_store_data_bypass_p (rtx, rtx);
extern rtx mips_prefetch_cookie (rtx, rtx);
extern void irix_asm_output_align (FILE *, unsigned);
extern const char *current_section_name (void);
extern unsigned int current_section_flags (void);
extern bool mips_use_ins_ext_p (rtx, rtx, rtx);
extern bool mips_use_ins_ext_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
extern const char *mips16e_output_save_restore (rtx, HOST_WIDE_INT);
extern bool mips16e_save_restore_pattern_p (rtx, HOST_WIDE_INT,
......
......@@ -61,7 +61,7 @@
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
FAIL;
gen_conditional_move (operands);
mips_expand_conditional_move (operands);
DONE;
})
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -922,7 +922,7 @@ enum mips_code_readable_setting {
#define SWITCH_TAKES_ARG(CHAR) \
(DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
#define OVERRIDE_OPTIONS override_options ()
#define OVERRIDE_OPTIONS mips_override_options ()
#define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
......@@ -1385,7 +1385,7 @@ enum mips_code_readable_setting {
Regarding coprocessor registers: without evidence to the contrary,
it's best to assume that each coprocessor register has a unique
use. This can be overridden, in, e.g., override_options() or
use. This can be overridden, in, e.g., mips_override_options or
CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
for a particular target. */
......@@ -1864,9 +1864,9 @@ enum reg_class
general registers, and from the floating point registers. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
mips_secondary_reload_class (CLASS, MODE, X, 1)
mips_secondary_reload_class (CLASS, MODE, X, true)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
mips_secondary_reload_class (CLASS, MODE, X, 0)
mips_secondary_reload_class (CLASS, MODE, X, false)
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
......@@ -1959,10 +1959,10 @@ enum reg_class
#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
#define LIBCALL_VALUE(MODE) \
mips_function_value (NULL_TREE, NULL, (MODE))
mips_function_value (NULL_TREE, MODE)
#define FUNCTION_VALUE(VALTYPE, FUNC) \
mips_function_value ((VALTYPE), (FUNC), VOIDmode)
mips_function_value (VALTYPE, VOIDmode)
/* 1 if N is a possible register number for a function value.
On the MIPS, R2 R3 and F0 F2 are the only register thus used.
......@@ -2002,9 +2002,9 @@ enum reg_class
allocate floating-point registers.
So for the standard ABIs, the first N words are allocated to integer
registers, and function_arg decides on an argument-by-argument basis
whether that argument should really go in an integer register, or in
a floating-point one. */
registers, and mips_function_arg decides on an argument-by-argument
basis whether that argument should really go in an integer register,
or in a floating-point one. */
typedef struct mips_args {
/* Always true for varargs functions. Otherwise true if at least
......@@ -2047,14 +2047,14 @@ typedef struct mips_args {
For a library call, FNTYPE is 0. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
mips_init_cumulative_args (&CUM, FNTYPE)
/* Update the data in CUM to advance over an argument
of mode MODE and data type TYPE.
(TYPE is null for libcalls where that information may not be available.) */
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
function_arg_advance (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
/* Determine where to put an argument to a function.
Value is zero to push the argument on the stack,
......@@ -2070,14 +2070,14 @@ typedef struct mips_args {
(otherwise it is an extra parameter matching an ellipsis). */
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
function_arg( &CUM, MODE, TYPE, NAMED)
mips_function_arg (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG_BOUNDARY function_arg_boundary
#define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
#define FUNCTION_ARG_PADDING(MODE, TYPE) \
#define FUNCTION_ARG_PADDING(MODE, TYPE) \
(mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
(mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
/* True if using EABI and varargs can be passed in floating-point
......@@ -2099,8 +2099,7 @@ typedef struct mips_args {
/* Implement `va_start' for varargs and stdarg. */
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
mips_va_start (valist, nextarg)
#define EXPAND_BUILTIN_VA_START mips_va_start
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. */
......@@ -2539,44 +2538,9 @@ typedef struct mips_args {
#define ALL_COP_ADDITIONAL_REGISTER_NAMES
/* A C compound statement to output to stdio stream STREAM the
assembler syntax for an instruction operand X. X is an RTL
expression.
CODE is a value that can be used to specify one of several ways
of printing the operand. It is used when identical operands
must be printed differently depending on the context. CODE
comes from the `%' specification that was used to request
printing of the operand. If the specification was just `%DIGIT'
then CODE is 0; if the specification was `%LTR DIGIT' then CODE
is the ASCII code for LTR.
If X is a register, this macro should print the register's name.
The names can be found in an array `reg_names' whose type is
`char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
When the machine description has a specification `%PUNCT' (a `%'
followed by a punctuation character), this macro is called with
a null pointer for X and the punctuation character for CODE.
See mips.c for the MIPS specific codes. */
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
/* A C expression which evaluates to true if CODE is a valid
punctuation character for use in the `PRINT_OPERAND' macro. If
`PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
punctuation characters (except for the standard one, `%') are
used in this way. */
#define PRINT_OPERAND mips_print_operand
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
/* A C compound statement to output to stdio stream STREAM the
assembler syntax for an instruction operand that is a memory
reference whose address is ADDR. ADDR is an RTL expression. */
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
#define PRINT_OPERAND_ADDRESS mips_print_operand_address
/* A C statement, to be executed after all slot-filler instructions
have been output. If necessary, call `dbr_sequence_length' to
......@@ -2608,10 +2572,8 @@ do \
} \
while (0)
/* How to tell the debugger about changes of source files. */
#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
mips_output_filename (STREAM, NAME)
#define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
/* mips-tfile does not understand .stabd directives. */
#define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
......@@ -2736,8 +2698,7 @@ do { \
/* This is how to output a string. */
#undef ASM_OUTPUT_ASCII
#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
#define ASM_OUTPUT_ASCII mips_output_ascii
/* Output #ident as a in the read-only data section. */
#undef ASM_OUTPUT_IDENT
......@@ -3038,16 +2999,12 @@ while (0)
#ifndef USED_FOR_TARGET
extern const enum reg_class mips_regno_to_class[];
extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
extern bool mips_print_operand_punct[256];
extern const char *current_function_file; /* filename current function is in */
extern int num_source_filenames; /* current .file # */
extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
extern int sym_lineno; /* sgi next label # for each stmt */
extern int set_noreorder; /* # of nested .set noreorder's */
extern int set_nomacro; /* # of nested .set nomacro's */
extern int set_noat; /* # of nested .set noat's */
extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
extern int mips_dbx_regno[];
extern int mips_dwarf_regno[];
extern bool mips_split_p[];
......@@ -3056,7 +3013,6 @@ extern enum processor_type mips_arch; /* which cpu to codegen for */
extern enum processor_type mips_tune; /* which cpu to schedule for */
extern int mips_isa; /* architectural level */
extern int mips_abi; /* which ABI to use */
extern const struct mips_cpu_info mips_cpu_info_table[];
extern const struct mips_cpu_info *mips_arch_info;
extern const struct mips_cpu_info *mips_tune_info;
extern const struct mips_rtx_cost_data *mips_cost;
......
......@@ -749,11 +749,10 @@
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
&& operands[1] == const0_rtx)
{
mips_gen_conditional_trap (operands);
mips_expand_conditional_trap (GET_CODE (operands[0]));
DONE;
}
else
FAIL;
FAIL;
})
(define_insn "*conditional_trap<mode>"
......@@ -3027,9 +3026,9 @@
(match_operand 3 "immediate_operand")))]
"!TARGET_MIPS16"
{
if (mips_expand_unaligned_load (operands[0], operands[1],
INTVAL (operands[2]),
INTVAL (operands[3])))
if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
INTVAL (operands[2]),
INTVAL (operands[3])))
DONE;
else
FAIL;
......@@ -3042,11 +3041,12 @@
(match_operand 3 "immediate_operand")))]
"!TARGET_MIPS16"
{
if (mips_expand_unaligned_load (operands[0], operands[1],
INTVAL (operands[2]),
INTVAL (operands[3])))
if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
INTVAL (operands[2]),
INTVAL (operands[3])))
DONE;
else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
INTVAL (operands[3])))
{
if (GET_MODE (operands[0]) == DImode)
emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
......@@ -3065,7 +3065,8 @@
(zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:SI 2 "immediate_operand" "I")
(match_operand:SI 3 "immediate_operand" "I")))]
"mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
"mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
INTVAL (operands[3]))"
"<d>ext\t%0,%1,%3,%2"
[(set_attr "type" "arith")
(set_attr "mode" "<MODE>")])
......@@ -3078,11 +3079,12 @@
(match_operand 3 "reg_or_0_operand"))]
"!TARGET_MIPS16"
{
if (mips_expand_unaligned_store (operands[0], operands[3],
INTVAL (operands[1]),
INTVAL (operands[2])))
if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
INTVAL (operands[1]),
INTVAL (operands[2])))
DONE;
else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
INTVAL (operands[2])))
{
if (GET_MODE (operands[0]) == DImode)
emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
......@@ -3101,7 +3103,8 @@
(match_operand:SI 1 "immediate_operand" "I")
(match_operand:SI 2 "immediate_operand" "I"))
(match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
"mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
"mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
INTVAL (operands[2]))"
"<d>ins\t%0,%z3,%2,%1"
[(set_attr "type" "arith")
(set_attr "mode" "<MODE>")])
......@@ -3343,7 +3346,7 @@
(set_attr "length" "4")])
;; Instructions for adding the low 16 bits of an address to a register.
;; Operand 2 is the address: print_operand works out which relocation
;; Operand 2 is the address: mips_print_operand works out which relocation
;; should be applied.
(define_insn "*low<mode>"
......@@ -3374,7 +3377,7 @@
""
[(const_int 0)]
{
mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
DONE;
})
......@@ -3680,7 +3683,7 @@
(clobber (match_operand:TF 2 "register_operand" "=&f"))]
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
{
mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
DONE;
})
......@@ -3690,7 +3693,7 @@
(clobber (match_operand:TF 2 "register_operand" "=&f"))]
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
{
mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
DONE;
})
......@@ -4658,7 +4661,7 @@
so, for a shift between 8 and 16, it is just as fast to do two
shifts of 8 or less. If there is a lot of shifting going on, we
may win in CSE. Otherwise combine will put the shifts back
together again. This can be called by function_arg, so we must
together again. This can be called by mips_function_arg, so we must
be careful not to allocate a new register if we've reached the
reload pass. */
if (TARGET_MIPS16
......@@ -5030,7 +5033,7 @@
(pc)))]
""
{
gen_conditional_branch (operands, <CODE>);
mips_expand_conditional_branch (operands, <CODE>);
DONE;
})
......@@ -5053,7 +5056,7 @@
(eq:SI (match_dup 1)
(match_dup 2)))]
""
{ if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
(define_insn "*seq_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5081,7 +5084,7 @@
(ne:SI (match_dup 1)
(match_dup 2)))]
"!TARGET_MIPS16"
{ if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
(define_insn "*sne_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5097,7 +5100,7 @@
(gt:SI (match_dup 1)
(match_dup 2)))]
""
{ if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (GT, operands[0])) DONE; else FAIL; })
(define_insn "*sgt_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5122,7 +5125,7 @@
(ge:SI (match_dup 1)
(match_dup 2)))]
""
{ if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (GE, operands[0])) DONE; else FAIL; })
(define_insn "*sge_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5138,7 +5141,7 @@
(lt:SI (match_dup 1)
(match_dup 2)))]
""
{ if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (LT, operands[0])) DONE; else FAIL; })
(define_insn "*slt_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5168,7 +5171,7 @@
(le:SI (match_dup 1)
(match_dup 2)))]
""
{ if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (LE, operands[0])) DONE; else FAIL; })
(define_insn "*sle_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5202,7 +5205,7 @@
(gtu:SI (match_dup 1)
(match_dup 2)))]
""
{ if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (GTU, operands[0])) DONE; else FAIL; })
(define_insn "*sgtu_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5227,7 +5230,7 @@
(geu:SI (match_dup 1)
(match_dup 2)))]
""
{ if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (GEU, operands[0])) DONE; else FAIL; })
(define_insn "*sge_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5243,7 +5246,7 @@
(ltu:SI (match_dup 1)
(match_dup 2)))]
""
{ if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (LTU, operands[0])) DONE; else FAIL; })
(define_insn "*sltu_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5273,7 +5276,7 @@
(leu:SI (match_dup 1)
(match_dup 2)))]
""
{ if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
{ if (mips_expand_scc (LEU, operands[0])) DONE; else FAIL; })
(define_insn "*sleu_<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
......@@ -5562,7 +5565,6 @@
emit_insn (gen_eh_set_lr_di (operands[0]));
else
emit_insn (gen_eh_set_lr_si (operands[0]));
DONE;
})
......@@ -5992,7 +5994,7 @@
(match_operand:GPR 3 "reg_or_0_operand")))]
"ISA_HAS_CONDMOVE"
{
gen_conditional_move (operands);
mips_expand_conditional_move (operands);
DONE;
})
......@@ -6004,7 +6006,7 @@
(match_operand:SCALARF 3 "register_operand")))]
"ISA_HAS_CONDMOVE"
{
gen_conditional_move (operands);
mips_expand_conditional_move (operands);
DONE;
})
......
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