Commit 651a7953 by Carl Love Committed by Carl Love

re PR target/86591 (gcc.target/powerpc/builtins-1.c fails starting with r261904)

gcc/testsuite/ChangeLog:

2018-07-23  Carl Love  <cel@us.ibm.com>

	PR 86591
	* gcc.target/powerpc/altivec-1-runnable.c: Move vector double tests to
	file altivec-2-runnable.c.
	* gcc.target/powerpc/altivec-2-runnable.c: Add vector double tests.
	* gcc.target/powerpc/buitlins-1.c: Remove dg-final check for xxlor.
	Update dg-final test for __divdi3 and __udivdi3 instructions. Update
	comments for instruction generated by vec_mergeh, vec_perm, vec_round,
	vec_cts, vec_ctu, vec_cpsgn tests.

From-SVN: r262934
parent 1544db9a
2018-07-23 Carl Love <cel@us.ibm.com>
PR 86591
* gcc.target/powerpc/altivec-1-runnable.c: Move vector double tests to
file altivec-2-runnable.c.
* gcc.target/powerpc/altivec-2-runnable.c: Add vector double tests.
* gcc.target/powerpc/buitlins-1.c: Remove dg-final check for xxlor.
Update dg-final test for __divdi3 and __udivdi3 instructions. Update
comments for instruction generated by vec_mergeh, vec_perm, vec_round,
vec_cts, vec_ctu, vec_cpsgn tests.
2018-07-23 Bernd Edlinger <bernd.edlinger@hotmail.de>
PR c/86617
......
......@@ -31,16 +31,9 @@ int main ()
vector signed int vec_si_result, vec_si_expected;
vector signed char vec_sc_arg;
vector signed char vec_sc_result, vec_sc_expected;
vector float vec_float_arg;
vector double vec_double_result, vec_double_expected;
vector pixel vec_pixel_arg;
vector unsigned int vec_ui_result, vec_ui_expected;
union conv {
double d;
unsigned long long l;
} conv_exp, conv_val;
vec_bs_arg = (vector bool short){ 0, 101, 202, 303,
404, 505, 606, 707 };
vec_bi_expected = (vector bool int){ 0, 101, 202, 303 };
......@@ -209,49 +202,6 @@ int main ()
abort();
#endif
}
vec_float_arg = (vector float){ 0.0, 1.5, 2.5, 3.5 };
vec_double_expected = (vector double){ 0.0, 1.5 };
vec_double_result = vec_unpackh (vec_float_arg);
for (i = 0; i < 2; i++) {
if (vec_double_expected[i] != vec_double_result[i])
{
#if DEBUG
printf("ERROR: vec_unpackh(), vec_double_expected[%d] = %f does not match vec_double_result[%d] = %f\n",
i, vec_double_expected[i], i, vec_double_result[i]);
conv_val.d = vec_double_result[i];
conv_exp.d = vec_double_expected[i];
printf(" vec_unpackh(), vec_double_expected[%d] = 0x%llx does not match vec_double_result[%d] = 0x%llx\n",
i, conv_exp.l, i,conv_val.l);
#else
abort();
#endif
}
}
vec_double_expected = (vector double){ 2.5, 3.5 };
vec_double_result = vec_unpackl (vec_float_arg);
for (i = 0; i < 2; i++) {
if (vec_double_expected[i] != vec_double_result[i])
{
#if DEBUG
printf("ERROR: vec_unpackl() vec_double_expected[%d] = %f does not match vec_double_result[%d] = %f\n",
i, vec_double_expected[i], i, vec_double_result[i]);
conv_val.d = vec_double_result[i];
conv_exp.d = vec_double_expected[i];
printf(" vec_unpackh(), vec_double_expected[%d] = 0x%llx does not match vec_double_result[%d] = 0x%llx\n",
i, conv_exp.l, i,conv_val.l);
#else
abort();
#endif
}
}
return 0;
}
......@@ -23,8 +23,15 @@ int main ()
vector signed int vec_si_arg;
vector signed long long int vec_slli_result, vec_slli_expected;
vector float vec_float_arg;
vector double vec_double_result, vec_double_expected;
/* use of ‘long long’ in AltiVec types requires -mvsx */
union conv {
double d;
unsigned long long l;
} conv_exp, conv_val;
/* Use of 'double' and ‘long long’ in AltiVec types requires -mvsx */
/* __builtin_altivec_vupkhsw and __builtin_altivec_vupklsw
requires the -mpower8-vector option */
......@@ -88,7 +95,47 @@ int main ()
#endif
}
vec_float_arg = (vector float){ 0.0, 1.5, 2.5, 3.5 };
vec_double_expected = (vector double){ 0.0, 1.5 };
vec_double_result = vec_unpackh (vec_float_arg);
for (i = 0; i < 2; i++) {
if (vec_double_expected[i] != vec_double_result[i])
{
#if DEBUG
printf("ERROR: vec_unpackh(), vec_double_expected[%d] = %f does not match vec_double_result[%d] = %f\n",
i, vec_double_expected[i], i, vec_double_result[i]);
conv_val.d = vec_double_result[i];
conv_exp.d = vec_double_expected[i];
printf(" vec_unpackh(), vec_double_expected[%d] = 0x%llx does not match vec_double_result[%d] = 0x%llx\n",
i, conv_exp.l, i,conv_val.l);
#else
abort();
#endif
}
}
vec_double_expected = (vector double){ 2.5, 3.5 };
vec_double_result = vec_unpackl (vec_float_arg);
for (i = 0; i < 2; i++) {
if (vec_double_expected[i] != vec_double_result[i])
{
#if DEBUG
printf("ERROR: vec_unpackl() vec_double_expected[%d] = %f does not match vec_double_result[%d] = %f\n",
i, vec_double_expected[i], i, vec_double_result[i]);
conv_val.d = vec_double_result[i];
conv_exp.d = vec_double_expected[i];
printf(" vec_unpackh(), vec_double_expected[%d] = 0x%llx does not match vec_double_result[%d] = 0x%llx\n",
i, conv_exp.l, i,conv_val.l);
#else
abort();
#endif
}
}
return 0;
}
......@@ -276,21 +276,20 @@ int main ()
vec_any_lt vcmpgtud.
vec_any_le vcmpgtud.
vec_and xxland
vec_andc xxland
vec_andc xxlandc
vec_cntlz vclzd, vclzb, vclzw, vclzh
xvcpsgnsp vec_cpsgn
vec_cpsgn xvcpsgnsp
vec_ctf xvmuldp
vec_cts xvcvdpsxds, vctsxs
vec_ctu xvcvdpuxds, vctuxs
vec_cts vctsxs
vec_ctu vctuxs
vec_div divd, divdu | __divdi3(), __udivdi3()
vec_mergel vmrghb, vmrghh, xxmrghw
vec_mergeh xxmrglw, vmrglh
vec_mergeh xxmrglw, vmrglh, vmrglb
vec_mul mulld | mullw, mulhwu
vec_nor xxlnor
vec_or xxlor
vec_packsu vpkudus
vec_ perm vperm
vec_ round xvrdpi
vec_perm vperm
vec_round xvrdpi
vec_sel xxsel
vec_xor xxlxor
vec_rsqrt xvrsqrtesp
......@@ -324,8 +323,6 @@ int main ()
/* { dg-final { scan-assembler-times "xxmrglw" 8 } } */
/* { dg-final { scan-assembler-times "vmrglh" 8 } } */
/* { dg-final { scan-assembler-times "xxlnor" 6 } } */
/* { dg-final { scan-assembler-times "xxlor" 11 { target { ilp32 } } } } */
/* { dg-final { scan-assembler-times "xxlor" 7 { target { lp64 } } } } */
/* { dg-final { scan-assembler-times {\mvpkudus\M} 1 } } */
/* { dg-final { scan-assembler-times "vperm" 4 } } */
/* { dg-final { scan-assembler-times "xvrdpi" 2 } } */
......@@ -334,8 +331,10 @@ int main ()
/* { dg-final { scan-assembler-times "divd" 8 { target lp64 } } } */
/* { dg-final { scan-assembler-times "divdu" 2 { target lp64 } } } */
/* { dg-final { scan-assembler-times "mulld" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times {\mbl __divdi3\M} 2 { target { ilp32 } } } } */
/* { dg-final { scan-assembler-times {\mbl __udivdi3\M} 2 { target {ilp32 } } } } */
/* check for both .__divdi3 (AIX) and __divdi3 (Linux) */
/* { dg-final { scan-assembler-times {\mbl \.?__divdi3\M} 2 { target { ilp32 } } } } */
/* check for both .__udivdi3 (AIX) and __udivdi3 (Linux) */
/* { dg-final { scan-assembler-times {\mbl \.?__udivdi3\M} 2 { target { ilp32 } } } } */
/* { dg-final { scan-assembler-times "mullw" 12 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "mulhwu" 4 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "xxmrgld" 0 } } */
......
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