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riscv-gcc-1
Commit 64bb2e1d by Richard Henderson Committed by Richard Henderson
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alpha.c (fix_operator): New. 

        * config/alpha/alpha.c (fix_operator): New.
        (divmod_operator): Tidy.
        (alpha_emit_xfloating_cvt): Handle UNSIGNED_FIX.
        * config/alpha/alpha.h (FIXUNS_TRUNC_LIKE_FIX_TRUNC): Remove.
        (PREDICATE_CODES): Update.
        * config/alpha/alpha.md (fix_truncdfsi_ieee): Use match_operator.
        (fix_truncdfsi_internal, fix_truncdfdi_ieee): Likewise.
        (fix_truncsfsi_ieee, fix_truncsfsi_internal): Likewise.
        (fix_truncsfdi_ieee): Likewise.
        (fix_truncdfdi2, fix_truncsfdi2): Turn into define_expand.
        (fixuns_truncdfdi2, fixuns_truncsfdi2, fixuns_trunctfdi2): New.
        * config/alpha/alpha-protos.h: Update.

From-SVN: r72677
parent 91999e1d
Showing with 100 additions and 42 deletions
gcc/ChangeLog
2003-10-19 Richard Henderson <rth@redhat.com>
* config/alpha/alpha.c (fix_operator): New.
(divmod_operator): Tidy.
(alpha_emit_xfloating_cvt): Handle UNSIGNED_FIX.
* config/alpha/alpha.h (FIXUNS_TRUNC_LIKE_FIX_TRUNC): Remove.
(PREDICATE_CODES): Update.
* config/alpha/alpha.md (fix_truncdfsi_ieee): Use match_operator.
(fix_truncdfsi_internal, fix_truncdfdi_ieee): Likewise.
(fix_truncsfsi_ieee, fix_truncsfsi_internal): Likewise.
(fix_truncsfdi_ieee): Likewise.
(fix_truncdfdi2, fix_truncsfdi2): Turn into define_expand.
(fixuns_truncdfdi2, fixuns_truncsfdi2, fixuns_trunctfdi2): New.
* config/alpha/alpha-protos.h: Update.
2003-10-19 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (INITIALIZE_TRAMPOLINE): Simplify.
......
gcc/config/alpha/alpha-protos.h
......@@ -75,6 +75,7 @@ extern int alpha_swapped_comparison_operator (rtx, enum machine_mode);
extern int signed_comparison_operator (rtx, enum machine_mode);
extern int alpha_fp_comparison_operator (rtx, enum machine_mode);
extern int divmod_operator (rtx, enum machine_mode);
extern int fix_operator (rtx, enum machine_mode);
extern int aligned_memory_operand (rtx, enum machine_mode);
extern int unaligned_memory_operand (rtx, enum machine_mode);
extern int reg_or_unaligned_mem_operand (rtx, enum machine_mode);
......
gcc/config/alpha/alpha.c
......@@ -1179,16 +1179,19 @@ alpha_fp_comparison_operator (rtx op, enum machine_mode mode)
int
divmod_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
switch (GET_CODE (op))
{
case DIV: case MOD: case UDIV: case UMOD:
return 1;
enum rtx_code code = GET_CODE (op);
default:
break;
}
return (code == DIV || code == MOD || code == UDIV || code == UMOD);
}
return 0;
/* Return 1 if this is a float->int conversion operator. */
int
fix_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
enum rtx_code code = GET_CODE (op);
return (code == FIX || code == UNSIGNED_FIX);
}
/* Return 1 if this memory address is a known aligned register plus
......@@ -3774,11 +3777,15 @@ alpha_emit_xfloating_compare (enum rtx_code code, rtx op0, rtx op1)
/* Emit an X_floating library function call for a conversion. */
void
alpha_emit_xfloating_cvt (enum rtx_code code, rtx operands[])
alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
{
int noperands = 1, mode;
rtx out_operands[2];
const char *func;
enum rtx_code code = orig_code;
if (code == UNSIGNED_FIX)
code = FIX;
func = alpha_lookup_xfloating_lib_func (code);
......@@ -3801,7 +3808,8 @@ alpha_emit_xfloating_cvt (enum rtx_code code, rtx operands[])
}
alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
gen_rtx_fmt_e (code, GET_MODE (operands[0]),
gen_rtx_fmt_e (orig_code,
GET_MODE (operands[0]),
operands[1]));
}
......
gcc/config/alpha/alpha.h
......@@ -1338,14 +1338,6 @@ do { \
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 1
/* This flag, if defined, says the same insns that convert to a signed fixnum
also convert validly to an unsigned one.
We actually lie a bit here as overflow conditions are different. But
they aren't being checked anyway. */
#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
/* Max number of bytes we can move to or from memory
in one reasonably fast instruction. */
......@@ -1654,6 +1646,7 @@ do { \
{"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
{"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
{"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
{"fix_operator", {FIX, UNSIGNED_FIX}}, \
{"const0_operand", {CONST_INT, CONST_DOUBLE, CONST_VECTOR}}, \
{"samegp_function_operand", {SYMBOL_REF}}, \
{"direct_call_operand", {SYMBOL_REF}}, \
......
gcc/config/alpha/alpha.md
......@@ -2337,13 +2337,15 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
(define_insn_and_split "*fix_truncdfsi_ieee"
[(set (match_operand:SI 0 "memory_operand" "=m")
(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
(subreg:SI
(match_operator:DI 4 "fix_operator"
[(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
(clobber (match_scratch:DI 2 "=&f"))
(clobber (match_scratch:SI 3 "=&f"))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"#"
"&& reload_completed"
[(set (match_dup 2) (fix:DI (match_dup 1)))
[(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 3))]
""
......@@ -2352,22 +2354,25 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
(define_insn_and_split "*fix_truncdfsi_internal"
[(set (match_operand:SI 0 "memory_operand" "=m")
(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
(subreg:SI
(match_operator:DI 3 "fix_operator"
[(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"#"
"&& reload_completed"
[(set (match_dup 2) (fix:DI (match_dup 1)))
(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 3))]
[(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
(set (match_dup 4) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 4))]
;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
"operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
"operands[4] = gen_rtx_REG (SImode, REGNO (operands[2]));"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn "*fix_truncdfdi_ieee"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
(fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
(match_operator:DI 2 "fix_operator"
[(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
......@@ -2375,9 +2380,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
(define_insn "fix_truncdfdi2"
(define_insn "*fix_truncdfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
(fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
(match_operator:DI 2 "fix_operator"
[(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
"TARGET_FP"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
......@@ -2385,18 +2391,32 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
(define_expand "fix_truncdfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "")
(fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
"TARGET_FP"
"")
(define_expand "fixuns_truncdfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "")
(unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
"TARGET_FP"
"")
;; Likewise between SFmode and SImode.
(define_insn_and_split "*fix_truncsfsi_ieee"
[(set (match_operand:SI 0 "memory_operand" "=m")
(subreg:SI (fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
(subreg:SI
(match_operator:DI 4 "fix_operator"
[(float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
(clobber (match_scratch:DI 2 "=&f"))
(clobber (match_scratch:SI 3 "=&f"))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"#"
"&& reload_completed"
[(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
[(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 3))]
""
......@@ -2405,24 +2425,26 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
(define_insn_and_split "*fix_truncsfsi_internal"
[(set (match_operand:SI 0 "memory_operand" "=m")
(subreg:SI (fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
(subreg:SI
(match_operator:DI 3 "fix_operator"
[(float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
(clobber (match_scratch:DI 2 "=f"))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"#"
"&& reload_completed"
[(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 3))]
[(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
(set (match_dup 4) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 0) (match_dup 4))]
;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
"operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
"operands[4] = gen_rtx_REG (SImode, REGNO (operands[2]));"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(define_insn "*fix_truncsfdi_ieee"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
(fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))))]
(match_operator:DI 2 "fix_operator"
[(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
......@@ -2430,10 +2452,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
(define_insn "fix_truncsfdi2"
(define_insn "*fix_truncsfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
(fix:DI (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))))]
(match_operator:DI 2 "fix_operator"
[(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
"TARGET_FP"
"cvt%-q%/ %R1,%0"
[(set_attr "type" "fadd")
......@@ -2441,12 +2463,31 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
(set_attr "round_suffix" "c")
(set_attr "trap_suffix" "v_sv_svi")])
(define_expand "fix_truncsfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "")
(fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
"TARGET_FP"
"")
(define_expand "fixuns_truncsfdi2"
[(set (match_operand:DI 0 "reg_no_subreg_operand" "")
(unsigned_fix:DI
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
"TARGET_FP"
"")
(define_expand "fix_trunctfdi2"
[(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FIX, operands); DONE;")
(define_expand "fixuns_trunctfdi2"
[(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
(define_insn "*floatdisf_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
......
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