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Commit 6485d5d6 by Kewen Lin
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[rs6000] vector conversion RTL pattern update for diff unit size 

2019-11-01  Kewen Lin  <linkw@gcc.gnu.org>

  * config/rs6000/rs6000-modes.def (V2SF, V2SI): New modes.
  * config/rs6000/vsx.md (UNSPEC_VSX_CVSPSXDS, UNSPEC_VSX_CVSPUXDS): Remove.
  (vsx_xvcvspdp): New define_expand, old define_insn split to...
  (vsx_xvcvspdp_be): ... this.  New.  And...
  (vsx_xvcvspdp_le): ... this.  New.
  (vsx_xvcv<su>xwdp): New define_expand, old define_insn split to...
  (vsx_xvcv<su>xwdp_be): ... this.  New.  And...
  (vsx_xvcv<su>xwdp_le): ... this.  New.
  (vsx_xvcvsp<su>xds): New define_expand, old define_insn split to...
  (vsx_xvcvsp<su>xds_be): ... this.  New.  And...
  (vsx_xvcvsp<su>xds_le): ... this.  New.

From-SVN: r277709
parent 4d8cfe0e
Showing with 102 additions and 31 deletions
gcc/ChangeLog
2019-11-01 Kewen Lin <linkw@gcc.gnu.org>
* config/rs6000/rs6000-modes.def (V2SF, V2SI): New modes.
* config/rs6000/vsx.md (UNSPEC_VSX_CVSPSXDS,
UNSPEC_VSX_CVSPUXDS): Remove.
(vsx_xvcvspdp): New define_expand, old define_insn split to...
(vsx_xvcvspdp_be): ... this. New. And...
(vsx_xvcvspdp_le): ... this. New.
(vsx_xvcv<su>xwdp): New define_expand, old define_insn split to...
(vsx_xvcv<su>xwdp_be): ... this. New. And...
(vsx_xvcv<su>xwdp_le): ... this. New.
(vsx_xvcvsp<su>xds): New define_expand, old define_insn split to...
(vsx_xvcvsp<su>xds_be): ... this. New. And...
(vsx_xvcvsp<su>xds_le): ... this. New.
2019-11-01 Kewen Lin <linkw@gcc.gnu.org>
* config/rs6000/vsx.md (UNSPEC_VSX_CVSXWSP, UNSPEC_VSX_CVUXWSP,
UNSPEC_VSX_XVCVSXDDP, UNSPEC_VSX_XVCVUXDDP,
UNSPEC_VSX_XVCVDPSXDS, UNSPEC_VSX_XVCVDPUXDS,
gcc/config/rs6000/rs6000-modes.def
......@@ -74,6 +74,10 @@ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
/* Half VMX/VSX vector (for internal use) */
VECTOR_MODE (FLOAT, SF, 2); /* V2SF */
VECTOR_MODE (INT, SI, 2); /* V2SI */
/* Replacement for TImode that only is allowed in GPRs. We also use PTImode
for quad memory atomic operations to force getting an even/odd register
combination. */
......
gcc/config/rs6000/vsx.md
......@@ -275,8 +275,6 @@
UNSPEC_VSX_CVUXWDP
UNSPEC_VSX_CVSXDSP
UNSPEC_VSX_CVUXDSP
UNSPEC_VSX_CVSPSXDS
UNSPEC_VSX_CVSPUXDS
UNSPEC_VSX_FLOAT2
UNSPEC_VSX_UNS_FLOAT2
UNSPEC_VSX_FLOATE
......@@ -2114,14 +2112,36 @@
"xscvdpsp %x0,%x1"
[(set_attr "type" "fp")])
(define_insn "vsx_xvcvspdp"
(define_insn "vsx_xvcvspdp_be"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
(unspec:V2DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
(float_extend:V2DF
(vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
(parallel [(const_int 0) (const_int 2)]))))]
"VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN"
"xvcvspdp %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvspdp_le"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
(float_extend:V2DF
(vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
(parallel [(const_int 1) (const_int 3)]))))]
"VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN"
"xvcvspdp %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_expand "vsx_xvcvspdp"
[(match_operand:V2DF 0 "vsx_register_operand")
(match_operand:V4SF 1 "vsx_register_operand")]
"VECTOR_UNIT_VSX_P (V4SFmode)"
{
if (BYTES_BIG_ENDIAN)
emit_insn (gen_vsx_xvcvspdp_be (operands[0], operands[1]));
else
emit_insn (gen_vsx_xvcvspdp_le (operands[0], operands[1]));
DONE;
})
(define_insn "vsx_xvcvdpsp"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "v,wa")]
......@@ -2341,16 +2361,39 @@
"xvcvuxdsp %x0,%x1"
[(set_attr "type" "vecdouble")])
;; Convert from 32-bit to 64-bit types
;; Provide both vector and scalar targets
(define_insn "vsx_xvcvsxwdp"
;; Convert vector of 32-bit signed/unsigned integers to vector of
;; 64-bit floating point numbers.
(define_insn "vsx_xvcv<su>xwdp_be"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSXWDP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvsxwdp %x0,%x1"
(any_float:V2DF
(vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa")
(parallel [(const_int 0) (const_int 2)]))))]
"VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
"xvcv<su>xwdp %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcv<su>xwdp_le"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
(any_float:V2DF
(vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa")
(parallel [(const_int 1) (const_int 3)]))))]
"VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN"
"xvcv<su>xwdp %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_expand "vsx_xvcv<su>xwdp"
[(match_operand:V2DF 0 "vsx_register_operand")
(match_operand:V4SI 1 "vsx_register_operand")
(any_float (pc))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
if (BYTES_BIG_ENDIAN)
emit_insn (gen_vsx_xvcv<su>xwdp_be (operands[0], operands[1]));
else
emit_insn (gen_vsx_xvcv<su>xwdp_le (operands[0], operands[1]));
DONE;
})
(define_insn "vsx_xvcvsxwdp_df"
[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
......@@ -2359,14 +2402,6 @@
"xvcvsxwdp %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvuxwdp"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVUXWDP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvuxwdp %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvuxwdp_df"
[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
......@@ -2375,22 +2410,39 @@
"xvcvuxwdp %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvspsxds"
;; Convert vector of 32-bit floating point numbers to vector of
;; 64-bit signed/unsigned integers.
(define_insn "vsx_xvcvsp<su>xds_be"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
(unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
UNSPEC_VSX_CVSPSXDS))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvspsxds %x0,%x1"
(any_fix:V2DI
(vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
(parallel [(const_int 0) (const_int 2)]))))]
"VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
"xvcvsp<su>xds %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvspuxds"
(define_insn "vsx_xvcvsp<su>xds_le"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
(unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
UNSPEC_VSX_CVSPUXDS))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvspuxds %x0,%x1"
(any_fix:V2DI
(vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
(parallel [(const_int 1) (const_int 3)]))))]
"VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN"
"xvcvsp<su>xds %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_expand "vsx_xvcvsp<su>xds"
[(match_operand:V2DI 0 "vsx_register_operand")
(match_operand:V4SF 1 "vsx_register_operand")
(any_fix (pc))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
if (BYTES_BIG_ENDIAN)
emit_insn (gen_vsx_xvcvsp<su>xds_be (operands[0], operands[1]));
else
emit_insn (gen_vsx_xvcvsp<su>xds_le (operands[0], operands[1]));
DONE;
})
;; Generate float2 double
;; convert two double to float
(define_expand "float2_v2df"
......
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