rs6000-protos.h: Rename output_e500_flip_eq_bit to output_e500_flip_gt_bit.

	* config/rs6000/rs6000-protos.h: Rename output_e500_flip_eq_bit to
	output_e500_flip_gt_bit.

	* config/rs6000/rs6000.c (print_operand): case D: Print out bit 31
	as bit 31.
	(rs6000_generate_compare): Fix logic to look at the correct bits.
	(output_e500_flip_eq_bit): Rename to output_e500_flip_gt_bit.
	Look at GT bit.
	(rs6000_emit_sCOND): Rename gen_e500_flip_eq_bit to
	gen_e500_flip_gt_bit.  Rename gen_move_from_CR_eq_bit to
	gen_move_from_CR_gt_bit.

	* config/rs6000/rs6000.md ("move_from_CR_eq_bit"): Change bit
	("move_from_CR_eq_bit"): Rename to move_from_CR_gt_bit.
	(UNSPEC_MV_CR_EQ): Rename to UNSPEC_MV_CR_GT.

	* config/rs6000/spe.md ("e500_cr_ior_compare"): New.
	(E500_CR_IOR_COMPARE): New constant.

[[Split portion of a mixed commit.]]

From-SVN: r96063.2

gcc/ChangeLog

+2005-03-07  Aldy Hernandez  <aldyh@redhat.com>
+
+	* config/rs6000/rs6000-protos.h: Rename output_e500_flip_eq_bit to
+	output_e500_flip_gt_bit.
+
+	* config/rs6000/rs6000.c (print_operand): case D: Print out bit 31
+	as bit 31.
+	(rs6000_generate_compare): Fix logic to look at the correct bits.
+	(output_e500_flip_eq_bit): Rename to output_e500_flip_gt_bit.
+	Look at GT bit.
+	(rs6000_emit_sCOND): Rename gen_e500_flip_eq_bit to
+	gen_e500_flip_gt_bit.  Rename gen_move_from_CR_eq_bit to
+	gen_move_from_CR_gt_bit.
+
+	* config/rs6000/rs6000.md ("move_from_CR_eq_bit"): Change bit
+	("move_from_CR_eq_bit"): Rename to move_from_CR_gt_bit.
+	(UNSPEC_MV_CR_EQ): Rename to UNSPEC_MV_CR_GT.
+
+	* config/rs6000/spe.md ("e500_cr_ior_compare"): New.
+	(E500_CR_IOR_COMPARE): New constant.
+
 2005-03-08  Earl Chew <earl_chew@agilent.com>
 	    David Billinghurst <David.Billinghurst@riotinto.com>
 

gcc/config/rs6000/rs6000-protos.h

@@ -76,7 +76,7 @@ extern enum rtx_code rs6000_reverse_condition (enum machine_mode,
 extern void rs6000_emit_sCOND (enum rtx_code, rtx);
 extern void rs6000_emit_cbranch (enum rtx_code, rtx);
 extern char * output_cbranch (rtx, const char *, int, rtx);
-extern char * output_e500_flip_eq_bit (rtx, rtx);
+extern char * output_e500_flip_gt_bit (rtx, rtx);
 extern rtx rs6000_emit_set_const (rtx, enum machine_mode, rtx, int);
 extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx);
 extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx);

gcc/config/rs6000/rs6000.c

@@ -9211,8 +9211,7 @@ print_operand (FILE *file, rtx x, int code)
       /* Bit 1 is EQ bit.  */
       i = 4 * (REGNO (x) - CR0_REGNO) + 2;
 
-      /* If we want bit 31, write a shift count of zero, not 32.  */
-      fprintf (file, "%d", i == 31 ? 0 : i + 1);
+      fprintf (file, "%d", i);
       return;
 
     case 'E':
@@ -10017,7 +10016,7 @@ rs6000_generate_compare (enum rtx_code code)
   if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
       && rs6000_compare_fp_p)
     {
-      rtx cmp, or1, or2, or_result, compare_result2;
+      rtx cmp, or_result, compare_result2;
       enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
 
       if (op_mode == VOIDmode)
@@ -10091,9 +10090,6 @@ rs6000_generate_compare (enum rtx_code code)
 	    default: abort ();
 	    }
 
-	  or1 = gen_reg_rtx (SImode);
-	  or2 = gen_reg_rtx (SImode);
-	  or_result = gen_reg_rtx (CCEQmode);
 	  compare_result2 = gen_reg_rtx (CCFPmode);
 
 	  /* Do the EQ.  */
@@ -10112,14 +10108,10 @@ rs6000_generate_compare (enum rtx_code code)
 	  else abort ();
 	  emit_insn (cmp);
 
-	  or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
-	  or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
-
 	  /* OR them together.  */
-	  cmp = gen_rtx_SET (VOIDmode, or_result,
-			     gen_rtx_COMPARE (CCEQmode,
-					      gen_rtx_IOR (SImode, or1, or2),
-					      const_true_rtx));
+	  or_result = gen_reg_rtx (CCFPmode);
+	  cmp = gen_e500_cr_ior_compare (or_result, compare_result,
+					   compare_result2);
 	  compare_result = or_result;
 	  code = EQ;
 	}
@@ -10229,9 +10221,9 @@ rs6000_emit_sCOND (enum rtx_code code, rtx result)
 	abort ();
 
       if (cond_code == NE)
-	emit_insn (gen_e500_flip_eq_bit (t, t));
+	emit_insn (gen_e500_flip_gt_bit (t, t));
 
-      emit_insn (gen_move_from_CR_eq_bit (result, t));
+      emit_insn (gen_move_from_CR_gt_bit (result, t));
       return;
     }
 
@@ -10412,9 +10404,9 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn)
   return string;
 }
 
-/* Return the string to flip the EQ bit on a CR.  */
+/* Return the string to flip the GT bit on a CR.  */
 char *
-output_e500_flip_eq_bit (rtx dst, rtx src)
+output_e500_flip_gt_bit (rtx dst, rtx src)
 {
   static char string[64];
   int a, b;
@@ -10423,9 +10415,9 @@ output_e500_flip_eq_bit (rtx dst, rtx src)
       || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
     abort ();
 
-  /* EQ bit.  */
-  a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
-  b = 4 * (REGNO (src) - CR0_REGNO) + 2;
+  /* GT bit.  */
+  a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
+  b = 4 * (REGNO (src) - CR0_REGNO) + 1;
 
   sprintf (string, "crnot %d,%d", a, b);
   return string;

gcc/config/rs6000/rs6000.md

@@ -50,7 +50,7 @@
    (UNSPEC_TLSGOTTPREL		28)
    (UNSPEC_TLSTLS		29)
    (UNSPEC_FIX_TRUNC_TF		30)	; fadd, rounding towards zero
-   (UNSPEC_MV_CR_EQ		31)	; move_from_CR_eq_bit
+   (UNSPEC_MV_CR_GT		31)	; move_from_CR_eq_bit
   ])
 
 ;;
@@ -11476,11 +11476,11 @@
    (set_attr "length" "8")])
 
 ;; Same as above, but get the GT bit.
-(define_insn "move_from_CR_eq_bit"
+(define_insn "move_from_CR_gt_bit"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))]
+	(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
   "TARGET_E500"
-  "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
+  "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
   [(set_attr "type" "mfcr")
    (set_attr "length" "8")])
 

gcc/config/rs6000/spe.md

@@ -29,6 +29,7 @@
    (TSTDFGT_GPR		1009)
    (CMPDFLT_GPR		1010)
    (TSTDFLT_GPR		1011)
+   (E500_CR_IOR_COMPARE 1012)
    ])
 
 (define_insn "*negsf2_gpr"
@@ -2615,14 +2616,14 @@
 ;; FP comparison stuff.
 
 ;; Flip the GT bit.
-(define_insn "e500_flip_eq_bit"
+(define_insn "e500_flip_gt_bit"
   [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
 	(unspec:CCFP
 	 [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
   "!TARGET_FPRS && TARGET_HARD_FLOAT"
   "*
 {
-  return output_e500_flip_eq_bit (operands[0], operands[1]);
+  return output_e500_flip_gt_bit (operands[0], operands[1]);
 }"
   [(set_attr "type" "cr_logical")])
 
@@ -2751,3 +2752,13 @@
   "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
   "efdtstlt %0,%1,%2"
   [(set_attr "type" "veccmpsimple")])
+
+;; Like cceq_ior_compare, but compare the GT bits.
+(define_insn "e500_cr_ior_compare"
+  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+	(unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
+		      (match_operand 2 "cc_reg_operand" "y")]
+		     E500_CR_IOR_COMPARE))]
+  "TARGET_E500"
+  "cror 4*%0+gt,4*%1+gt,4*%2+gt"
+  [(set_attr "type" "cr_logical")])