[NDS32] Implement n7 pipeline.

gcc/
	* config.gcc (nds32*-*-*): Check that n7 is valid to --with-cpu.
	* config/nds32/nds32-n7.md: New file.
	* config/nds32/nds32-opts.h (nds32_cpu_type): Add CPU_N7.
	* config/nds32/nds32-pipelines-auxiliary.c: Implementation for n7
	pipeline.
	* config/nds32/nds32-protos.h: More declarations for n7 pipeline.
	* config/nds32/nds32.md (pipeline_model): Add n7.
	* config/nds32/nds32.opt (mcpu): Support n7 pipeline cpus.
	* config/nds32/pipelines.md: Include n7 settings.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>

From-SVN: r259221

gcc/ChangeLog

 2018-04-08  Kito Cheng  <kito.cheng@gmail.com>
 	    Chung-Ju Wu  <jasonwucj@gmail.com>
 
+	* config.gcc (nds32*-*-*): Check that n7 is valid to --with-cpu.
+	* config/nds32/nds32-n7.md: New file.
+	* config/nds32/nds32-opts.h (nds32_cpu_type): Add CPU_N7.
+	* config/nds32/nds32-pipelines-auxiliary.c: Implementation for n7
+	pipeline.
+	* config/nds32/nds32-protos.h: More declarations for n7 pipeline.
+	* config/nds32/nds32.md (pipeline_model): Add n7.
+	* config/nds32/nds32.opt (mcpu): Support n7 pipeline cpus.
+	* config/nds32/pipelines.md: Include n7 settings.
+
+2018-04-08  Kito Cheng  <kito.cheng@gmail.com>
+	    Chung-Ju Wu  <jasonwucj@gmail.com>
+
 	* config.gcc (nds32*-*-*): Check that e8 is valid to --with-cpu.
 	* config/nds32/nds32-e8.md: New file.
 	* config/nds32/nds32-opts.h (nds32-cpu_type): Add CPU_E8.

gcc/config.gcc

@@ -4315,11 +4315,11 @@ case "${target}" in
 		"")
 			with_cpu=n9
 			;;
-		n6 | n8 | e8 | s8 | n9)
+		n6 | n7 | n8 | e8 | s8 | n9)
 			# OK
 			;;
 		*)
-			echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n8 e8 s8 n9" 1>&2
+			echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n7 n8 e8 s8 n9" 1>&2
 			exit 1
 			;;
 		esac

gcc/config/nds32/nds32-opts.h

@@ -38,6 +38,7 @@ enum nds32_arch_type
 enum nds32_cpu_type
 {
   CPU_N6,
+  CPU_N7,
   CPU_N8,
   CPU_E8,
   CPU_N9,

gcc/config/nds32/nds32-pipelines-auxiliary.c

@@ -344,6 +344,98 @@ using namespace nds32;
 using namespace nds32::scheduling;
 
 namespace { // anonymous namespace
+
+/* Check the dependency between the producer defining DEF_REG and CONSUMER
+   requiring input operand at II.  */
+bool
+n7_consumed_by_ii_dep_p (rtx_insn *consumer, rtx def_reg)
+{
+  rtx use_rtx;
+
+  switch (get_attr_type (consumer))
+    {
+    /* MOVD44_E */
+    case TYPE_ALU:
+      if (movd44_even_dep_p (consumer, def_reg))
+	return true;
+
+      use_rtx = SET_SRC (PATTERN (consumer));
+      break;
+
+    case TYPE_MUL:
+      use_rtx = SET_SRC (PATTERN (consumer));
+      break;
+
+    case TYPE_MAC:
+      use_rtx = extract_mac_non_acc_rtx (consumer);
+      break;
+
+   /* Some special instructions, divmodsi4 and udivmodsi4, produce two
+      results, the quotient and the remainder.  It requires two micro-
+      operations in order to write two registers. We have to check the
+      dependency from the producer to the first micro-operation.  */
+    case TYPE_DIV:
+      if (INSN_CODE (consumer) == CODE_FOR_divmodsi4
+	  || INSN_CODE (consumer) == CODE_FOR_udivmodsi4)
+	use_rtx = SET_SRC (parallel_element (consumer, 0));
+      else
+	use_rtx = SET_SRC (PATTERN (consumer));
+      break;
+
+    case TYPE_LOAD:
+      /* ADDR_IN_bi_Ra, ADDR_IN_!bi */
+      if (post_update_insn_p (consumer))
+	use_rtx = extract_base_reg (consumer);
+      else
+	use_rtx = extract_mem_rtx (consumer);
+      break;
+
+    case TYPE_STORE:
+      /* ADDR_IN_bi_Ra, ADDR_IN_!bi */
+      if (post_update_insn_p (consumer))
+	use_rtx = extract_base_reg (consumer);
+      else
+	use_rtx = extract_mem_rtx (consumer);
+
+      if (reg_overlap_p (def_reg, use_rtx))
+	return true;
+
+      /* ST_bi, ST_!bi_RI */
+      if (!post_update_insn_p (consumer)
+	  && !immed_offset_p (extract_mem_rtx (consumer)))
+	return false;
+
+      use_rtx = SET_SRC (PATTERN (consumer));
+      break;
+
+    case TYPE_LOAD_MULTIPLE:
+      use_rtx = extract_base_reg (consumer);
+      break;
+
+    case TYPE_STORE_MULTIPLE:
+      /* ADDR_IN */
+      use_rtx = extract_base_reg (consumer);
+      if (reg_overlap_p (def_reg, use_rtx))
+	return true;
+
+      /* SMW (N, 1) */
+      use_rtx = extract_nth_access_rtx (consumer, 0);
+      break;
+
+    case TYPE_BRANCH:
+      use_rtx = PATTERN (consumer);
+      break;
+
+    default:
+      gcc_unreachable ();
+    }
+
+  if (reg_overlap_p (def_reg, use_rtx))
+    return true;
+
+  return false;
+}
+
 /* Check the dependency between the producer defining DEF_REG and CONSUMER
    requiring input operand at AG (II).  */
 bool
@@ -657,6 +749,39 @@ n9_3r2w_consumed_by_ex_dep_p (rtx_insn *consumer, rtx def_reg)
 
 /* ------------------------------------------------------------------------ */
 
+/* Guard functions for N7 core.  */
+
+bool
+nds32_n7_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
+{
+  if (post_update_insn_p (producer))
+    return false;
+
+  rtx def_reg = SET_DEST (PATTERN (producer));
+
+  return n7_consumed_by_ii_dep_p (consumer, def_reg);
+}
+
+bool
+nds32_n7_last_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
+{
+  /* If PRODUCER is a post-update LMW insn, the last micro-operation updates
+     the base register and the result is ready in II stage, so we don't need
+     to handle that case in this guard function and the corresponding bypass
+     rule.  */
+  if (post_update_insn_p (producer))
+    return false;
+
+  rtx last_def_reg = extract_nth_access_reg (producer, -1);
+
+  if (last_def_reg == NULL_RTX)
+    return false;
+
+  gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+
+  return n7_consumed_by_ii_dep_p (consumer, last_def_reg);
+}
+
 /* Guard functions for N8 core.  */
 
 bool

gcc/config/nds32/nds32-protos.h

@@ -99,6 +99,9 @@ extern bool nds32_valid_multiple_load_store_p (rtx, bool, bool);
 
 /* Auxiliary functions for guard function checking in pipelines.md.  */
 
+extern bool nds32_n7_load_to_ii_p (rtx_insn *, rtx_insn *);
+extern bool nds32_n7_last_load_to_ii_p (rtx_insn *, rtx_insn *);
+
 extern bool nds32_n8_load_to_ii_p (rtx_insn *, rtx_insn *);
 extern bool nds32_n8_load_bi_to_ii_p (rtx_insn *, rtx_insn *);
 extern bool nds32_n8_load_to_ex_p (rtx_insn *, rtx_insn *);

gcc/config/nds32/nds32.md

@@ -56,9 +56,10 @@
 ;; ------------------------------------------------------------------------
 
 ;; CPU pipeline model.
-(define_attr "pipeline_model" "n8,e8,n9,simple"
+(define_attr "pipeline_model" "n7,n8,e8,n9,simple"
   (const
-    (cond [(match_test "nds32_cpu_option == CPU_E8")  (const_string "e8")
+    (cond [(match_test "nds32_cpu_option == CPU_N7")  (const_string "n7")
+	   (match_test "nds32_cpu_option == CPU_E8")  (const_string "e8")
 	   (match_test "nds32_cpu_option == CPU_N6 || nds32_cpu_option == CPU_N8")  (const_string "n8")
 	   (match_test "nds32_cpu_option == CPU_N9")  (const_string "n9")
 	   (match_test "nds32_cpu_option == CPU_SIMPLE") (const_string "simple")]

gcc/config/nds32/nds32.opt

@@ -181,6 +181,12 @@ EnumValue
 Enum(nds32_cpu_type) String(n650) Value(CPU_N6)
 
 EnumValue
+Enum(nds32_cpu_type) String(n7) Value(CPU_N7)
+
+EnumValue
+Enum(nds32_cpu_type) String(n705) Value(CPU_N7)
+
+EnumValue
 Enum(nds32_cpu_type) String(n8) Value(CPU_N8)
 
 EnumValue

gcc/config/nds32/pipelines.md

@@ -19,6 +19,12 @@
 ;; <http://www.gnu.org/licenses/>.
 
 ;; ------------------------------------------------------------------------
+;; Include N7 pipeline settings.
+;; ------------------------------------------------------------------------
+(include "nds32-n7.md")
+
+
+;; ------------------------------------------------------------------------
 ;; Include N8 pipeline settings.
 ;; ------------------------------------------------------------------------
 (include "nds32-n8.md")