[NDS32] Implment n15 pipeline.

gcc/
	* config.gcc (nds32*-*-*): Check that n15 is valid to --with-cpu.
	* config/nds32/nds32-graywolf.md: New file.
	* config/nds32/nds32-opts.h (nds32_cpu_type): Add CPU_GRAYWOLF.
	* config/nds32/nds32-pipelines-auxiliary.c: Implementation for n15
	pipeline.
	* config/nds32/nds32-protos.h: More declarations for n15 pipeline.
	* config/nds32/nds32-utils.c: More implementations for n15 pipeline.
	* config/nds32/nds32.md (pipeline_model): Add graywolf.
	* config/nds32/nds32.opt (mcpu): Support n15 pipeline cpus.
	* config/nds32/pipelines.md: Include n15 settings.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>

From-SVN: r260214

gcc/ChangeLog

 2018-05-13  Kito Cheng  <kito.cheng@gmail.com>
 	    Chung-Ju Wu  <jasonwucj@gmail.com>
 
+	* config.gcc (nds32*-*-*): Check that n15 is valid to --with-cpu.
+	* config/nds32/nds32-graywolf.md: New file.
+	* config/nds32/nds32-opts.h (nds32_cpu_type): Add CPU_GRAYWOLF.
+	* config/nds32/nds32-pipelines-auxiliary.c: Implementation for n15
+	pipeline.
+	* config/nds32/nds32-protos.h: More declarations for n15 pipeline.
+	* config/nds32/nds32-utils.c: More implementations for n15 pipeline.
+	* config/nds32/nds32.md (pipeline_model): Add graywolf.
+	* config/nds32/nds32.opt (mcpu): Support n15 pipeline cpus.
+	* config/nds32/pipelines.md: Include n15 settings.
+
+2018-05-13  Kito Cheng  <kito.cheng@gmail.com>
+	    Chung-Ju Wu  <jasonwucj@gmail.com>
+
 	* config.gcc (nds32*-*-*): Check that n12/n13 are valid to --with-cpu.
 	* config/nds32/nds32-n13.md: New file.
 	* config/nds32/nds32-opts.h (nds32_cpu_type): Add CPU_N12 and CPU_N13.

gcc/config.gcc

@@ -4367,11 +4367,11 @@ case "${target}" in
 		"")
 			with_cpu=n9
 			;;
-		n6 | n7 |n8 | e8 | s8 | n9 | n10 | d10 | n12 | n13)
+		n6 | n7 |n8 | e8 | s8 | n9 | n10 | d10 | n12 | n13 | n15)
 			# OK
 			;;
 		*)
-			echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n7 n8 e8 s8 n9 n10 d10 n12 n13" 1>&2
+			echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n7 n8 e8 s8 n9 n10 d10 n12 n13 n15" 1>&2
 			exit 1
 			;;
 		esac

gcc/config/nds32/nds32-opts.h

@@ -43,6 +43,7 @@ enum nds32_cpu_type
   CPU_E8,
   CPU_N9,
   CPU_N10,
+  CPU_GRAYWOLF,
   CPU_N12,
   CPU_N13,
   CPU_SIMPLE

gcc/config/nds32/nds32-pipelines-auxiliary.c

@@ -931,6 +931,88 @@ n10_consumed_by_ex_dep_p (rtx_insn *consumer, rtx def_reg)
   return false;
 }
 
+/* Check the dependency between the producer defining DEF_REG and CONSUMER
+   requiring input operand at EX.  */
+bool
+gw_consumed_by_ex_dep_p (rtx_insn *consumer, rtx def_reg)
+{
+  rtx use_rtx;
+
+  switch (get_attr_type (consumer))
+    {
+    case TYPE_ALU:
+    case TYPE_PBSAD:
+    case TYPE_MUL:
+    case TYPE_DALU:
+    case TYPE_DALU64:
+    case TYPE_DMUL:
+    case TYPE_DPACK:
+    case TYPE_DINSB:
+    case TYPE_DCMP:
+    case TYPE_DCLIP:
+    case TYPE_DALUROUND:
+      use_rtx = SET_SRC (PATTERN (consumer));
+      break;
+
+    case TYPE_ALU_SHIFT:
+      use_rtx = extract_shift_reg (consumer);
+      break;
+
+    case TYPE_PBSADA:
+      return pbsada_insn_ra_rb_dep_reg_p (consumer, def_reg);
+
+    case TYPE_MAC:
+    case TYPE_DMAC:
+      use_rtx = extract_mac_non_acc_rtx (consumer);
+      break;
+
+   /* Some special instructions, divmodsi4 and udivmodsi4, produce two
+      results, the quotient and the remainder.  We have to check the
+      dependency from the producer to the first micro-operation.  */
+    case TYPE_DIV:
+      if (divmod_p (consumer))
+	use_rtx = SET_SRC (parallel_element (consumer, 0));
+      else
+	use_rtx = SET_SRC (PATTERN (consumer));
+      break;
+
+    case TYPE_DWEXT:
+      return wext_odd_dep_p (consumer, def_reg);
+
+    case TYPE_DBPICK:
+      return bpick_ra_rb_dep_p (consumer, def_reg);
+
+    case TYPE_MMU:
+      if (GET_CODE (PATTERN (consumer)) == SET)
+	use_rtx = SET_SRC (PATTERN (consumer));
+      else
+	return true;
+      break;
+
+    case TYPE_LOAD:
+    case TYPE_STORE:
+      use_rtx = extract_mem_rtx (consumer);
+      break;
+
+    case TYPE_LOAD_MULTIPLE:
+    case TYPE_STORE_MULTIPLE:
+      use_rtx = extract_base_reg (consumer);
+      break;
+
+    case TYPE_BRANCH:
+      use_rtx = PATTERN (consumer);
+      break;
+
+    default:
+      gcc_unreachable ();
+    }
+
+  if (reg_overlap_p (def_reg, use_rtx))
+    return true;
+
+  return false;
+}
+
 /* Check dependencies from any stages to ALU_E1 (E1).  This is a helper
    function of n13_consumed_by_e1_dep_p ().  */
 bool
@@ -1532,6 +1614,67 @@ nds32_n10_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
   return n10_consumed_by_ex_dep_p (consumer, last_def_reg);
 }
 
+/* Guard functions for Graywolf cores.  */
+
+/* Check dependencies from EX to EX (ADDR_OUT -> ADDR_IN).  */
+bool
+nds32_gw_ex_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
+{
+  return nds32_n10_ex_to_ex_p (producer, consumer);
+}
+
+/* Check dependencies from MM to EX.  */
+bool
+nds32_gw_mm_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
+{
+  rtx def_reg;
+
+  switch (get_attr_type (producer))
+    {
+    case TYPE_LOAD:
+    case TYPE_MUL:
+    case TYPE_MAC:
+    case TYPE_DALU64:
+    case TYPE_DMUL:
+    case TYPE_DMAC:
+    case TYPE_DALUROUND:
+    case TYPE_DBPICK:
+    case TYPE_DWEXT:
+      def_reg = SET_DEST (PATTERN (producer));
+      break;
+
+   /* Some special instructions, divmodsi4 and udivmodsi4, produce two
+      results, the quotient and the remainder.  We have to handle them
+      individually.  */
+    case TYPE_DIV:
+      if (divmod_p (producer))
+	{
+	  rtx def_reg1 = SET_DEST (parallel_element (producer, 0));
+	  rtx def_reg2 = SET_DEST (parallel_element (producer, 1));
+
+	  return (gw_consumed_by_ex_dep_p (consumer, def_reg1)
+		  || gw_consumed_by_ex_dep_p (consumer, def_reg2));
+	}
+
+      def_reg = SET_DEST (PATTERN (producer));
+      break;
+
+    default:
+      gcc_unreachable ();
+    }
+
+    return gw_consumed_by_ex_dep_p (consumer, def_reg);
+}
+
+/* Check dependencies from LMW(N, N) to EX.  */
+bool
+nds32_gw_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
+{
+  rtx last_def_reg = extract_nth_access_reg (producer, -1);
+
+  return gw_consumed_by_ex_dep_p (consumer, last_def_reg);
+}
+
 /* Guard functions for N12/N13 cores.  */
 
 /* Check dependencies from E2 to E1.  */

gcc/config/nds32/nds32-protos.h

@@ -125,6 +125,10 @@ extern bool nds32_n10_ex_to_ex_p (rtx_insn *, rtx_insn *);
 extern bool nds32_n10_mm_to_ex_p (rtx_insn *, rtx_insn *);
 extern bool nds32_n10_last_load_to_ex_p (rtx_insn *, rtx_insn *);
 
+extern bool nds32_gw_ex_to_ex_p (rtx_insn *, rtx_insn *);
+extern bool nds32_gw_mm_to_ex_p (rtx_insn *, rtx_insn *);
+extern bool nds32_gw_last_load_to_ex_p (rtx_insn *, rtx_insn *);
+
 extern bool nds32_n13_e2_to_e1_p (rtx_insn *, rtx_insn *);
 extern bool nds32_n13_load_to_e1_p (rtx_insn *, rtx_insn *);
 extern bool nds32_n13_load_to_e2_p (rtx_insn *, rtx_insn *);
@@ -297,11 +301,13 @@ bool load_single_p (rtx_insn *);
 bool store_single_p (rtx_insn *);
 bool load_double_p (rtx_insn *);
 bool store_double_p (rtx_insn *);
+bool store_offset_reg_p (rtx_insn *);
 bool post_update_insn_p (rtx_insn *);
 bool immed_offset_p (rtx);
 int find_post_update_rtx (rtx_insn *);
 rtx extract_mem_rtx (rtx_insn *);
 rtx extract_base_reg (rtx_insn *);
+rtx extract_offset_rtx (rtx_insn *);
 
 rtx extract_shift_reg (rtx);
 

gcc/config/nds32/nds32-utils.c

@@ -142,6 +142,23 @@ store_double_p (rtx_insn *insn)
   return true;
 }
 
+bool
+store_offset_reg_p (rtx_insn *insn)
+{
+  if (get_attr_type (insn) != TYPE_STORE)
+    return false;
+
+  rtx offset_rtx = extract_offset_rtx (insn);
+
+  if (offset_rtx == NULL_RTX)
+    return false;
+
+  if (REG_P (offset_rtx))
+    return true;
+
+  return false;
+}
+
 /* Determine if INSN is a post update insn.  */
 bool
 post_update_insn_p (rtx_insn *insn)
@@ -316,22 +333,114 @@ extract_base_reg (rtx_insn *insn)
   if (REG_P (XEXP (mem_rtx, 0)))
     return XEXP (mem_rtx, 0);
 
+  /* (mem (lo_sum (reg) (symbol_ref)) */
+  if (GET_CODE (XEXP (mem_rtx, 0)) == LO_SUM)
+    return XEXP (XEXP (mem_rtx, 0), 0);
+
   plus_rtx = XEXP (mem_rtx, 0);
 
   if (GET_CODE (plus_rtx) == SYMBOL_REF
       || GET_CODE (plus_rtx) == CONST)
     return NULL_RTX;
 
-  gcc_assert (GET_CODE (plus_rtx) == PLUS
-	      || GET_CODE (plus_rtx) == POST_INC
-	      || GET_CODE (plus_rtx) == POST_DEC
-	      || GET_CODE (plus_rtx) == POST_MODIFY);
-  gcc_assert (REG_P (XEXP (plus_rtx, 0)));
   /* (mem (plus (reg) (const_int))) or
+     (mem (plus (mult (reg) (const_int 4)) (reg))) or
      (mem (post_inc (reg))) or
      (mem (post_dec (reg))) or
      (mem (post_modify (reg) (plus (reg) (reg))))  */
-  return XEXP (plus_rtx, 0);
+  gcc_assert (GET_CODE (plus_rtx) == PLUS
+	      || GET_CODE (plus_rtx) == POST_INC
+	      || GET_CODE (plus_rtx) == POST_DEC
+	      || GET_CODE (plus_rtx) == POST_MODIFY);
+
+  if (REG_P (XEXP (plus_rtx, 0)))
+    return XEXP (plus_rtx, 0);
+
+  gcc_assert (REG_P (XEXP (plus_rtx, 1)));
+  return XEXP (plus_rtx, 1);
+}
+
+/* Extract the offset rtx from load/store insns.  The function returns
+   NULL_RTX if offset is absent.  */
+rtx
+extract_offset_rtx (rtx_insn *insn)
+{
+  rtx mem_rtx;
+  rtx plus_rtx;
+  rtx offset_rtx;
+
+  /* Find the MEM rtx.  The multiple load/store insns doens't have
+     the offset field so we can return NULL_RTX here.  */
+  switch (get_attr_type (insn))
+    {
+    case TYPE_LOAD_MULTIPLE:
+    case TYPE_STORE_MULTIPLE:
+      return NULL_RTX;
+
+    case TYPE_LOAD:
+    case TYPE_FLOAD:
+    case TYPE_STORE:
+    case TYPE_FSTORE:
+      mem_rtx = extract_mem_rtx (insn);
+      break;
+
+    default:
+      gcc_unreachable ();
+    }
+
+  gcc_assert (MEM_P (mem_rtx));
+
+  /* (mem (reg))  */
+  if (REG_P (XEXP (mem_rtx, 0)))
+    return NULL_RTX;
+
+  plus_rtx = XEXP (mem_rtx, 0);
+
+  switch (GET_CODE (plus_rtx))
+    {
+    case SYMBOL_REF:
+    case CONST:
+    case POST_INC:
+    case POST_DEC:
+      return NULL_RTX;
+
+    case PLUS:
+      /* (mem (plus (reg) (const_int))) or
+         (mem (plus (mult (reg) (const_int 4)) (reg))) */
+      if (REG_P (XEXP (plus_rtx, 0)))
+        offset_rtx = XEXP (plus_rtx, 1);
+      else
+	{
+	  gcc_assert (REG_P (XEXP (plus_rtx, 1)));
+	  offset_rtx = XEXP (plus_rtx, 0);
+	}
+
+      if (ARITHMETIC_P (offset_rtx))
+	{
+	  gcc_assert (GET_CODE (offset_rtx) == MULT);
+	  gcc_assert (REG_P (XEXP (offset_rtx, 0)));
+	  offset_rtx = XEXP (offset_rtx, 0);
+	}
+      break;
+
+    case LO_SUM:
+      /* (mem (lo_sum (reg) (symbol_ref)) */
+      offset_rtx = XEXP (plus_rtx, 1);
+      break;
+
+    case POST_MODIFY:
+      /* (mem (post_modify (reg) (plus (reg) (reg / const_int)))) */
+      gcc_assert (REG_P (XEXP (plus_rtx, 0)));
+      plus_rtx = XEXP (plus_rtx, 1);
+      gcc_assert (GET_CODE (plus_rtx) == PLUS);
+      offset_rtx = XEXP (plus_rtx, 0);
+      break;
+
+    default:
+      gcc_unreachable ();
+    }
+
+  return offset_rtx;
 }
 
 /* Extract the register of the shift operand from an ALU_SHIFT rtx.  */

gcc/config/nds32/nds32.md

@@ -56,13 +56,14 @@
 ;; ------------------------------------------------------------------------
 
 ;; CPU pipeline model.
-(define_attr "pipeline_model" "n7,n8,e8,n9,n10,n13,simple"
+(define_attr "pipeline_model" "n7,n8,e8,n9,n10,graywolf,n13,simple"
   (const
     (cond [(match_test "nds32_cpu_option == CPU_N7")  (const_string "n7")
 	   (match_test "nds32_cpu_option == CPU_E8")  (const_string "e8")
 	   (match_test "nds32_cpu_option == CPU_N6 || nds32_cpu_option == CPU_N8")  (const_string "n8")
 	   (match_test "nds32_cpu_option == CPU_N9")  (const_string "n9")
 	   (match_test "nds32_cpu_option == CPU_N10") (const_string "n10")
+	   (match_test "nds32_cpu_option == CPU_GRAYWOLF") (const_string "graywolf")
 	   (match_test "nds32_cpu_option == CPU_N12") (const_string "n13")
 	   (match_test "nds32_cpu_option == CPU_N13") (const_string "n13")
 	   (match_test "nds32_cpu_option == CPU_SIMPLE") (const_string "simple")]

gcc/config/nds32/nds32.opt

@@ -288,6 +288,27 @@ EnumValue
 Enum(nds32_cpu_type) String(d1088-spu) Value(CPU_N10)
 
 EnumValue
+Enum(nds32_cpu_type) Undocumented String(graywolf) Value(CPU_GRAYWOLF)
+
+EnumValue
+Enum(nds32_cpu_type) String(n15) Value(CPU_GRAYWOLF)
+
+EnumValue
+Enum(nds32_cpu_type) String(d15) Value(CPU_GRAYWOLF)
+
+EnumValue
+Enum(nds32_cpu_type) String(n15s) Value(CPU_GRAYWOLF)
+
+EnumValue
+Enum(nds32_cpu_type) String(d15s) Value(CPU_GRAYWOLF)
+
+EnumValue
+Enum(nds32_cpu_type) String(n15f) Value(CPU_GRAYWOLF)
+
+EnumValue
+Enum(nds32_cpu_type) String(d15f) Value(CPU_GRAYWOLF)
+
+EnumValue
 Enum(nds32_cpu_type) String(n12) Value(CPU_N12)
 
 EnumValue

gcc/config/nds32/pipelines.md

@@ -50,6 +50,12 @@
 
 
 ;; ------------------------------------------------------------------------
+;; Include Graywolf pipeline settings.
+;; ------------------------------------------------------------------------
+(include "nds32-graywolf.md")
+
+
+;; ------------------------------------------------------------------------
 ;; Include N12/N13 pipeline settings.
 ;; ------------------------------------------------------------------------
 (include "nds32-n13.md")