rs6000.md (define_constants): Define constants for all UNSPEC usage, including…

rs6000.md (define_constants): Define constants for all UNSPEC usage, including new values for TLS support.

2003-04-14  Janis Johnson  <janis187@us.ibm.com>

	* config/rs6000/rs6000.md (define_constants): Define constants for
	all UNSPEC usage, including new values for TLS support.
	(aux_truncdfsf2, fctiwz, movsi_got, movsi_got_internal,
	load_toc_aix_si, load_toc_aix_di, load_toc_v4_pic_si,
	load_toc_v4_PIC_1, load_toc_v4_PIC_1b, load_macho_picbase,
	macho_correct_pic, blockage, move_from_CR_ov_bit, movesi_from_cr,
	stack_tie, movsi_to_cr_one, movsi_to_cr, mtcrfsi, eh_set_lr_si,
	eh_set_lr_di): Use them.
	* rs6000.c: (mtcrf_operation, uses_TOC, rs6000_emit_prologue,
	rs6000_emit_epilogue) Use them.

From-SVN: r65604

gcc/ChangeLog

 2003-04-14  Janis Johnson  <janis287@us.ibm.com>
 
+	* config/rs6000/rs6000.md (define_constants): Define constants for
+	all UNSPEC usage, including new values for TLS support.
+	(aux_truncdfsf2, fctiwz, movsi_got, movsi_got_internal,
+	load_toc_aix_si, load_toc_aix_di, load_toc_v4_pic_si,
+	load_toc_v4_PIC_1, load_toc_v4_PIC_1b, load_macho_picbase,
+	macho_correct_pic, blockage, move_from_CR_ov_bit, movesi_from_cr,
+	stack_tie, movsi_to_cr_one, movsi_to_cr, mtcrfsi, eh_set_lr_si,
+	eh_set_lr_di): Use them.
+	* rs6000.c: (mtcrf_operation, uses_TOC, rs6000_emit_prologue,
+	rs6000_emit_epilogue) Use them.
+
 	* rtl.h (SYMBOL_REF_TLS_MODEL): Fix mask value.
 
 2003-04-14  Neil Booth  <neil@daikokuya.co.uk>

gcc/config/rs6000/rs6000.c

@@ -6789,7 +6789,7 @@ mtcrf_operation (op, mode)
       maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
       
       if (GET_CODE (unspec) != UNSPEC
-	  || XINT (unspec, 1) != 20
+	  || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
 	  || XVECLEN (unspec, 0) != 2
 	  || XVECEXP (unspec, 0, 0) != src_reg
 	  || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
@@ -10026,8 +10026,8 @@ get_TOC_alias_set ()
 }   
 
 /* This retuns nonzero if the current function uses the TOC.  This is
-   determined by the presence of (unspec ... 7), which is generated by
-   the various load_toc_* patterns.  */
+   determined by the presence of (unspec ... UNSPEC_TOC), which is
+   generated by the various load_toc_* patterns.  */
 
 int
 uses_TOC () 
@@ -10043,7 +10043,7 @@ uses_TOC ()
 	  if (GET_CODE (pat) == PARALLEL) 
 	    for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
 	      if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC 
-		 && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7)
+		 && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == UNSPEC_TOC)
 		  return 1;
 	}
     return 0;
@@ -10884,9 +10884,9 @@ rs6000_emit_prologue ()
       insn = emit_move_insn (mem, cr_save_rtx);
 
       /* Now, there's no way that dwarf2out_frame_debug_expr is going
-	 to understand '(unspec:SI [(reg:CC 68) ...] 19)'.  But that's
-	 OK.  All we have to do is specify that _one_ condition code
-	 register is saved in this stack slot.  The thrower's epilogue
+	 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
+	 But that's OK.  All we have to do is specify that _one_ condition
+	 code register is saved in this stack slot.  The thrower's epilogue
 	 will then restore all the call-saved registers.
 	 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux.  */
       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 
@@ -11287,7 +11287,7 @@ rs6000_emit_epilogue (sibcall)
 		RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
 		RTVEC_ELT (p, ndx) =
 		  gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), 
-			       gen_rtx_UNSPEC (CCmode, r, 20));
+			       gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
 		ndx++;
 	      }
 	  emit_insn (gen_rtx_PARALLEL (VOIDmode, p));

gcc/config/rs6000/rs6000.md

@@ -22,20 +22,43 @@
 
 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
 
-;; `unspec' values used in rs6000.md:
-;; Number	Use
-;; 0		frsp for POWER machines
-;; 0/v		blockage
-;; 5		used to tie the stack contents and the stack pointer
-;; 6		address of a word pointing to the TOC
-;; 7		address of the TOC (more-or-less)
-;; 8		movsi_got
-;; 9/v		eh_reg_restore
-;; 10		fctiwz
-;; 15		load_macho_picbase
-;; 16		macho_correct_pic
-;; 19		movesi_from_cr
-;; 20		movsi_to_cr
+;;
+;; UNSPEC usage
+;;
+
+(define_constants
+  [(UNSPEC_FRSP			0)	; frsp for POWER machines
+   (UNSPEC_TIE			5)	; tie stack contents and stack pointer
+   (UNSPEC_TOCPTR		6)	; address of a word pointing to the TOC
+   (UNSPEC_TOC			7)	; address of the TOC (more-or-less)
+   (UNSPEC_MOVSI_GOT		8)
+   (UNSPEC_MV_CR_OV		9)	; move_from_CR_ov_bit
+   (UNSPEC_FCTIWZ		10)
+   (UNSPEC_LD_MPIC		15)	; load_macho_picbase
+   (UNSPEC_MPIC_CORRECT		16)	; macho_correct_pic
+   (UNSPEC_TLSGD		17)
+   (UNSPEC_TLSLD		18)
+   (UNSPEC_MOVESI_FROM_CR	19)
+   (UNSPEC_MOVESI_TO_CR		20)
+   (UNSPEC_TLSDTPREL		21)
+   (UNSPEC_TLSDTPRELHA		22)
+   (UNSPEC_TLSDTPRELLO		23)
+   (UNSPEC_TLSGOTDTPREL		24)
+   (UNSPEC_TLSTPREL		25)
+   (UNSPEC_TLSTPRELHA		26)
+   (UNSPEC_TLSTPRELLO		27)
+   (UNSPEC_TLSGOTTPREL		28)
+   (UNSPEC_TLSTLS		29)
+  ])
+
+;;
+;; UNSPEC_VOLATILE usage
+;;
+
+(define_constants
+  [(UNSPECV_BLOCK		0)
+   (UNSPECV_EH_RR		9)	; eh_reg_restore
+  ])
 
 ;; Define an insn type attribute.  This is used in function unit delay
 ;; computations.
@@ -4362,7 +4385,7 @@
 
 (define_insn "aux_truncdfsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
+	(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
   "frsp %0,%1"
   [(set_attr "type" "fp")])
@@ -5148,13 +5171,14 @@
   DONE;
 }")
 
-; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10))
+; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
 ; because the first makes it clear that operand 0 is not live
 ; before the instruction.
 (define_insn "fctiwz"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
-	(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
+	(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
+		   UNSPEC_FCTIWZ))]
   "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
   "{fcirz|fctiwz} %0,%1"
   [(set_attr "type" "fp")])
@@ -7497,7 +7521,7 @@
 (define_expand "movsi_got"
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(unspec:SI [(match_operand:SI 1 "got_operand" "")
-		    (match_dup 2)] 8))]
+		    (match_dup 2)] UNSPEC_MOVSI_GOT))]
   "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
   "
 {
@@ -7523,7 +7547,8 @@
 (define_insn "*movsi_got_internal"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
-		    (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
+		    (match_operand:SI 2 "gpc_reg_operand" "b")]
+		   UNSPEC_MOVSI_GOT))]
   "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
   "{l|lwz} %0,%a1@got(%2)"
   [(set_attr "type" "load")])
@@ -7533,12 +7558,14 @@
 (define_split 
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
-		    (match_operand:SI 2 "memory_operand" "")] 8))]
+		    (match_operand:SI 2 "memory_operand" "")]
+		   UNSPEC_MOVSI_GOT))]
   "DEFAULT_ABI == ABI_V4
     && flag_pic == 1
     && (reload_in_progress || reload_completed)"
   [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))]
+   (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
+				 UNSPEC_MOVSI_GOT))]
   "")
 
 ;; For SI, we special-case integers that can't be loaded in one insn.  We
@@ -9820,7 +9847,7 @@
 
 (define_insn "load_toc_aix_si"
   [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-		   (unspec:SI [(const_int 0)] 7))
+		   (unspec:SI [(const_int 0)] UNSPEC_TOC))
 	      (use (reg:SI 2))])]
   "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
   "*
@@ -9835,7 +9862,7 @@
 
 (define_insn "load_toc_aix_di"
   [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-		   (unspec:DI [(const_int 0)] 7))
+		   (unspec:DI [(const_int 0)] UNSPEC_TOC))
 	      (use (reg:DI 2))])]
   "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
   "*
@@ -9857,7 +9884,7 @@
 
 (define_insn "load_toc_v4_pic_si"
   [(set (match_operand:SI 0 "register_operand" "=l")
-	(unspec:SI [(const_int 0)] 7))]
+	(unspec:SI [(const_int 0)] UNSPEC_TOC))]
   "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
   "bl _GLOBAL_OFFSET_TABLE_@local-4"
   [(set_attr "type" "branch")
@@ -9866,7 +9893,7 @@
 (define_insn "load_toc_v4_PIC_1"
   [(set (match_operand:SI 0 "register_operand" "=l")
 	(match_operand:SI 1 "immediate_operand" "s"))
-   (unspec [(match_dup 1)] 7)]
+   (unspec [(match_dup 1)] UNSPEC_TOC)]
   "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
   "bcl 20,31,%1\\n%1:"
   [(set_attr "type" "branch")
@@ -9875,7 +9902,8 @@
 (define_insn "load_toc_v4_PIC_1b"
   [(set (match_operand:SI 0 "register_operand" "=l")
 	(match_operand:SI 1 "immediate_operand" "s"))
-   (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
+   (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
+   	   UNSPEC_TOCPTR)]
   "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
   "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:"
   [(set_attr "type" "branch")
@@ -9892,7 +9920,8 @@
 
 (define_insn "load_macho_picbase"
   [(set (match_operand:SI 0 "register_operand" "=l")
-	(unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 15))]
+	(unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
+		   UNSPEC_LD_MPIC))]
   "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
   "bcl 20,31,%1\\n%1:"
   [(set_attr "type" "branch")
@@ -9903,7 +9932,7 @@
 	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
 			     (match_operand:SI 3 "immediate_operand" "s")]
-			    16)))]
+			    UNSPEC_MPIC_CORRECT)))]
   "DEFAULT_ABI == ABI_DARWIN"
   "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
   [(set_attr "length" "8")])
@@ -10689,7 +10718,7 @@
 ;; all of memory.  This blocks insns from being moved across this point.
 
 (define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
+  [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
   ""
   "")
 
@@ -11115,7 +11144,7 @@
 ;; Same as above, but get the OV/ORDERED bit.
 (define_insn "move_from_CR_ov_bit"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] 724))]
+	(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
   "TARGET_ISEL"
   "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
   [(set_attr "type" "mfcr")
@@ -14177,7 +14206,8 @@
 (define_insn "movesi_from_cr"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
         (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) 
-		    (reg:CC 72)	(reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
+		    (reg:CC 72)	(reg:CC 73) (reg:CC 74) (reg:CC 75)]
+		   UNSPEC_MOVESI_FROM_CR))]
   ""
   "mfcr %0"
   [(set_attr "type" "mfcr")])
@@ -14211,7 +14241,7 @@
 ; not be moved over stores to stack memory.
 (define_insn "stack_tie"
   [(set (match_operand:BLK 0 "memory_operand" "+m")
-        (unspec:BLK [(match_dup 0)] 5))]
+        (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
   ""
   ""
   [(set_attr "length" "0")])
@@ -14233,7 +14263,7 @@
 (define_expand "movsi_to_cr_one"
   [(set (match_operand:CC 0 "cc_reg_operand" "=y")
         (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
-		    (match_dup 2)] 20))]
+		    (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
   ""
   "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
 
@@ -14242,7 +14272,7 @@
 		   [(set (match_operand:CC 1 "cc_reg_operand" "=y")
 			 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
 				     (match_operand 3 "immediate_operand" "n")]
-			 20))])]
+				    UNSPEC_MOVESI_TO_CR))])]
  ""
  "*
 {
@@ -14258,7 +14288,8 @@
 (define_insn "*mtcrfsi"
   [(set (match_operand:CC 0 "cc_reg_operand" "=y")
         (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
-		    (match_operand 2 "immediate_operand" "n")] 20))]
+		    (match_operand 2 "immediate_operand" "n")]
+		   UNSPEC_MOVESI_TO_CR))]
   "GET_CODE (operands[0]) == REG 
    && CR_REGNO_P (REGNO (operands[0]))
    && GET_CODE (operands[2]) == CONST_INT
@@ -14334,19 +14365,21 @@
 
 ; We can't expand this before we know where the link register is stored.
 (define_insn "eh_set_lr_si"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9)
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
+  		    UNSPECV_EH_RR)
    (clobber (match_scratch:SI 1 "=&b"))]
   "TARGET_32BIT"
   "#")
 
 (define_insn "eh_set_lr_di"
-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9)
+  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
+  		    UNSPECV_EH_RR)
    (clobber (match_scratch:DI 1 "=&b"))]
   "TARGET_64BIT"
   "#")
 
 (define_split
-  [(unspec_volatile [(match_operand 0 "register_operand" "")] 9)
+  [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
    (clobber (match_scratch 1 ""))]
   "reload_completed"
   [(const_int 0)]