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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
61314cb4
Commit
61314cb4
authored
Dec 07, 1994
by
Richard Kenner
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New pattern for ior between SImode target and zero_extended value.
From-SVN: r8624
parent
9e8730a4
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gcc/config/m68k/m68k.md
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61314cb4
...
...
@@ -3194,6 +3194,25 @@
(match_dup 0)))]
""
"or%.b %1,%0")
(define_insn ""
[
(set (match_operand:SI 0 "general_operand" "=o,d")
(ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
(match_operand:SI 2 "general_operand" "0,0")))]
""
"
*
{
int byte_mode;
CC_STATUS_INIT;
byte_mode = (GET_MODE(operands
[
1
]
) == QImode);
if (GET_CODE (operands
[
0
]
) == MEM)
operands
[
0
]
= adj_offsettable_operand (operands
[
0
]
, byte_mode ? 3 : 2);
if (byte_mode)
return
\"
or%.b %1,%0
\"
;
else
return
\"
or%.w %1,%0
\"
;
}")
;; xor instructions
...
...
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