x32: Encode %esp as %rsp to avoid 0x67 prefix

Since the upper 32 bits of stack register are always zero for x32, we
can encode %esp as %rsp to avoid 0x67 prefix in address if there is no
index or base register.

gcc/

	PR target/82267
	* config/i386/i386.c (ix86_print_operand_address_as): Encode
	%esp as %rsp to avoid 0x67 prefix if there is no index or base
	register.

gcc/testsuite/

	PR target/82267
	* gcc.target/i386/pr82267.c: New test.

From-SVN: r253127

gcc/ChangeLog

+2017-09-24  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/82267
+	* config/i386/i386.c (ix86_print_operand_address_as): Encode
+	%esp as %rsp to avoid 0x67 prefix if there is no index or base
+	register.
+
 2017-09-23  Uros Bizjak  <ubizjak@gmail.com>
 
 	PR bootstrap/82306

gcc/config/i386/i386.c

@@ -19953,6 +19953,14 @@ ix86_print_operand_address_as (FILE *file, rtx addr,
 	  code = 'k';
 	}
 
+      /* Since the upper 32 bits of RSP are always zero for x32, we can
+	 encode %esp as %rsp to avoid 0x67 prefix if there is no index or
+	 base register.  */
+      if (TARGET_X32 && Pmode == SImode
+	  && ((!index && base && REGNO (base) == SP_REG)
+	      || (!base && index && REGNO (index) == SP_REG)))
+	code = 'q';
+
       if (ASSEMBLER_DIALECT == ASM_ATT)
 	{
 	  if (disp)

gcc/testsuite/ChangeLog

+2017-09-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/82267
+	* gcc.target/i386/pr82267.c: New test.
+
 2017-09-24  Thomas Koenig  <tkoenig@gcc.gnu.org>
 	PR fortran/66328
 

gcc/testsuite/gcc.target/i386/pr82267.c

+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-options "-O2 -mx32 -maddress-mode=short" } */
+
+int
+stackuse (void)
+{
+  volatile int foo = 2;
+  return foo * 3;
+}
+
+/* Verify we that use %rsp to access stack.  */
+/* { dg-final { scan-assembler-not "%esp" } } */
+/* { dg-final { scan-assembler "%rsp" } } */