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lvzhengyang
riscv-gcc-1
Commits
5fb12879
Commit
5fb12879
authored
Sep 30, 2003
by
Richard Earnshaw
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* arm/ieee754-sf.S: Tidy formatting.
From-SVN: r71941
parent
6a436e5e
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gcc/ChangeLog
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gcc/config/arm/ieee754-sf.S
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gcc/ChangeLog
View file @
5fb12879
2003-09-30
Nicolas Pitre <nico@cam.org
>
2003-09-30
Richard Earnshaw <rearnsha@arm.com
>
* arm/lib1funcs.asm (ARM_DIV_MOD_BODY) split into ARM_DIV_BODY
* arm/ieee754-sf.S: Tidy formatting.
2003-09-30 Nicolas Pitre <nico@cam.org>
* arm/lib1funcs.asm (ARM_DIV_MOD_BODY): Split into ARM_DIV_BODY
and ARM_MOD_BODY.
and ARM_MOD_BODY.
(ARM_MOD_BODY):
r
ewritten. added clz insns for __ARM_ARCH__ >= 5.
(ARM_MOD_BODY):
R
ewritten. added clz insns for __ARM_ARCH__ >= 5.
(ARM_DIV_BODY):
a
dded clz insns for __ARM_ARCH__ >= 5,
(ARM_DIV_BODY):
A
dded clz insns for __ARM_ARCH__ >= 5,
added better divisor alignment in the other case.
added better divisor alignment in the other case.
(ARM_DIV2_ORDER):
a
dded, finds the order of a single bit divisor.
(ARM_DIV2_ORDER):
A
dded, finds the order of a single bit divisor.
(__divsi3, __udivsi3, __modsi3, __umodsi3): rewritten using the
(__divsi3, __udivsi3, __modsi3, __umodsi3): rewritten using the
macros above, add fast exits for divisor >= dividend, etc.
macros above, add fast exits for divisor >= dividend, etc.
2003-09-30 Nicolas Pitre <nico@cam.org>
2003-09-30 Nicolas Pitre
<nico@cam.org>
* arm/ieee754-df.S:
s
plit compilation of fixunsdfsi from
* arm/ieee754-df.S:
S
plit compilation of fixunsdfsi from
L_fixdfsi target.
L_fixdfsi target.
* arm/t-arm-elf
: add _fixunsdfsi target due to the above
.
* arm/t-arm-elf
(LIB1ASMFUNCS): Add _fixunsdfsi
.
2003-09-30 Nathanael Nerode <neroden@gcc.gnu.org>
2003-09-30 Nathanael Nerode <neroden@gcc.gnu.org>
...
...
gcc/config/arm/ieee754-sf.S
View file @
5fb12879
...
@@ -396,7 +396,8 @@ LSYM(Lml_x):
...
@@ -396,7 +396,8 @@ LSYM(Lml_x):
RET
RET
@ Result is 0, but determine sign anyway.
@ Result is 0, but determine sign anyway.
LSYM(Lml_z): eor r0, r0, r1
LSYM(Lml_z):
eor r0, r0, r1
bic r0, r0, #0x7fffffff
bic r0, r0, #0x7fffffff
RET
RET
...
...
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