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riscv-gcc-1
Commit 5f90a099 by Jan Hubicka Committed by Jan Hubicka
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i386.md (movsi/movdi): Fix template. 

	* i386.md (movsi/movdi): Fix template.
	(sse2 patterns): Set attributes consistently.

	* i386.md (pushqi2, ashrqi_*): Fix constraint.

From-SVN: r53598
parent 6835a09c
Showing with 40 additions and 20 deletions
gcc/ChangeLog
Sun May 19 00:24:23 CEST 2002 Jan HUbicka <jh@suse.cz>
* i386.md (movsi/movdi): Fix template.
(sse2 patterns): Set attributes consistently.
* i386.md (pushqi2, ashrqi_*): Fix constraint.
2002-05-18 Toon Moene <toon@moene.indiv.nluug.nl>
* optabs.c (complex_part_zero_p): New.
......
gcc/config/i386/i386.md
......@@ -1092,12 +1092,12 @@
{
switch (get_attr_type (insn))
{
case TYPE_SSE:
case TYPE_SSEMOV:
if (get_attr_mode (insn) == TImode)
return "movdqa\t{%1, %0|%0, %1}";
return "movd\t{%1, %0|%0, %1}";
case TYPE_MMX:
case TYPE_MMXMOV:
if (get_attr_mode (insn) == DImode)
return "movq\t{%1, %0|%0, %1}";
return "movd\t{%1, %0|%0, %1}";
......@@ -1361,7 +1361,7 @@
;; For 64BIT abi we always round up to 8 bytes.
(define_insn "*pushqi2_rex64"
[(set (match_operand:QI 0 "push_operand" "=X")
(match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))]
(match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
"TARGET_64BIT"
"push{q}\t%q1"
[(set_attr "type" "push")
......@@ -1860,12 +1860,12 @@
{
switch (get_attr_type (insn))
{
case TYPE_SSE:
case TYPE_SSEMOV:
if (register_operand (operands[0], DImode)
&& register_operand (operands[1], DImode))
return "movdqa\t{%1, %0|%0, %1}";
/* FALLTHRU */
case TYPE_MMX:
case TYPE_MMXMOV:
return "movq\t{%1, %0|%0, %1}";
case TYPE_MULTI:
return "#";
......@@ -11184,7 +11184,7 @@
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const_int_1_operand" "I"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashiftrt:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& (TARGET_PENTIUM || TARGET_PENTIUMPRO)
......@@ -11205,7 +11205,7 @@
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "immediate_operand" "I"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashiftrt:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
......@@ -18026,7 +18026,8 @@
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"pand\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sselog")
(set_attr "mode" "TI")])
(define_insn "*sse_nandti3_df"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
......@@ -18061,7 +18062,8 @@
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pandn\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")])
[(set_attr "type" "sselog")
(set_attr "mode" "TI")])
(define_insn "sse2_nandv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
......@@ -18070,7 +18072,8 @@
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"pandn\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sselog")
(set_attr "mode" "TI")])
(define_insn "*sse_iorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
......@@ -18135,7 +18138,8 @@
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"por\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sselog")
(set_attr "mode" "TI")])
(define_insn "*sse_xorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
......@@ -18200,7 +18204,8 @@
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"pxor\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sselog")
(set_attr "mode" "TI")])
;; Use xor, but don't show input operands so they aren't live before
;; this insn.
......@@ -20602,7 +20607,8 @@
(match_operand:SI 2 "nonmemory_operand" "ri")))]
"TARGET_SSE2"
"pslld\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_insn "ashlv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
......@@ -20610,7 +20616,8 @@
(match_operand:SI 2 "nonmemory_operand" "ri")))]
"TARGET_SSE2"
"psllq\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_insn "ashrv8hi3_ti"
[(set (match_operand:V8HI 0 "register_operand" "=x")
......@@ -20618,7 +20625,8 @@
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psraw\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_insn "ashrv4si3_ti"
[(set (match_operand:V4SI 0 "register_operand" "=x")
......@@ -20626,7 +20634,8 @@
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psrad\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_insn "lshrv8hi3_ti"
[(set (match_operand:V8HI 0 "register_operand" "=x")
......@@ -20634,7 +20643,8 @@
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psrlw\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_insn "lshrv4si3_ti"
[(set (match_operand:V4SI 0 "register_operand" "=x")
......@@ -20642,7 +20652,8 @@
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psrld\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_insn "lshrv2di3_ti"
[(set (match_operand:V2DI 0 "register_operand" "=x")
......@@ -20650,7 +20661,8 @@
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psrlq\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_insn "ashlv8hi3_ti"
[(set (match_operand:V8HI 0 "register_operand" "=x")
......@@ -20658,7 +20670,8 @@
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psllw\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")])
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_insn "ashlv4si3_ti"
[(set (match_operand:V4SI 0 "register_operand" "=x")
......
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