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lvzhengyang
riscv-gcc-1
Commits
5f7d2979
Commit
5f7d2979
authored
Jul 08, 2005
by
Ian Lance Taylor
Committed by
Ian Lance Taylor
Jul 08, 2005
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* config/mips/mips.md (abs<mode>2) [GPR]: Remove.
From-SVN: r101752
parent
a0e71127
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gcc/ChangeLog
View file @
5f7d2979
2005-07-07 Ian Lance Taylor <ian@airs.com>
* config/mips/mips.md (abs<mode>2) [GPR]: Remove.
2005-07-07 John David Anglin <dave.anglin@nrc-crc.gc.ca>
PR middle-end/22239
...
...
gcc/config/mips/mips.md
View file @
5f7d2979
...
...
@@ -1898,20 +1898,6 @@
;; exception on -2147483648 (sigh).
(define_insn "abs
<mode>
2"
[
(set (match_operand:GPR 0 "register_operand" "=d")
(abs:GPR (match_operand:GPR 1 "register_operand" "d")))]
"!TARGET_MIPS16"
{
if (REGNO (operands
[
0
]
) == REGNO (operands
[
1
]
) && GENERATE_BRANCHLIKELY)
return "%(bltzl
\t
%1,1f
\;
<d>
subu
\t
%0,%.,%0
\n
%~1:%)";
else
return "%(bgez
\t
%1,1f
\;
move
\t
%0,%1
\;
<d>
subu
\t
%0,%.,%0
\n
%~1:%)";
}
[
(set_attr "type" "multi")
(set_attr "mode" "
<MODE>
")
(set_attr "length" "12")])
(define_insn "abs
<mode>
2"
[
(set (match_operand:ANYF 0 "register_operand" "=f")
(abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
""
...
...
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