Skip to content

R
riscv-gcc-1
Commit 5f732aba by David Edelsohn
Options

rs6000.c (struct processor_cost): Change l1_cache_lines to l1_cache_size. 

	* config/rs6000/rs6000.c (struct processor_cost): Change
	l1_cache_lines to l1_cache_size.  Add l2_cache_size.
	(*_cost): Convert l1 cache information to kilobytes.  Add l2 cache
	information.
	(rios1_costs, rios2_cost): Correct cache line size.
	(rs6000_override_options): Set l2-cache-size parameter.

From-SVN: r127181
parent 737b0891
Showing with 61 additions and 28 deletions
gcc/ChangeLog
2007-08-03 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.c (struct processor_cost): Change
l1_cache_lines to l1_cache_size. Add l2_cache_size.
(*_cost): Convert l1 cache information to kilobytes. Add l2 cache
information.
(rios1_costs, rios2_cost): Correct cache line size.
(rs6000_override_options): Set l2-cache-size parameter.
2007-08-03 Andrew Pinski <andrew_pinski@playstation.sony.com>
Diego Novillo <dnovillo@google.com>
......@@ -20529,7 +20538,7 @@
* langhooks.h (struct lang_hooks): Removed field
'can_use_bit_fields_p'.
2007-01-10 Ralf Corsépius <ralf.corsepius@rtems.org>
2007-01-10 Ralf Cors©pius <ralf.corsepius@rtems.org>
* config/bfin/t-bfin, config/bfin/t-bfin-elf: Remove GCC_CFLAGS.
......@@ -20758,7 +20767,7 @@
* config/frv/predicates.md (reg_or_0_operand): Accept
CONST_DOUBLEs.
2007-01-08 Ralf Corsépius <ralf.corsepius@rtems.org>
2007-01-08 Ralf Cors©pius <ralf.corsepius@rtems.org>
* config/bfin/rtems.h, config/bfin/t-rtems: New.
* config.gcc: Add bfin*-rtems*.
......
gcc/config/rs6000/rs6000.c
......@@ -289,8 +289,9 @@ struct processor_costs {
const int dmul; /* cost of DFmode multiplication (and fmadd). */
const int sdiv; /* cost of SFmode division (fdivs). */
const int ddiv; /* cost of DFmode division (fdiv). */
const int cache_line_size; /* cache block in bytes. */
const int l1_cache_lines; /* number of lines in L1 cache. */
const int cache_line_size; /* cache line size in bytes. */
const int l1_cache_size; /* size of l1 cache, in kilobytes. */
const int l2_cache_size; /* size of l2 cache, in kilobytes. */
const int simultaneous_prefetches; /* number of parallel prefetch
operations. */
};
......@@ -315,6 +316,7 @@ struct processor_costs size32_cost = {
32,
0,
0,
0,
};
/* Instruction size costs on 64bit processors. */
......@@ -333,6 +335,7 @@ struct processor_costs size64_cost = {
128,
0,
0,
0,
};
/* Instruction costs on RIOS1 processors. */
......@@ -348,8 +351,9 @@ struct processor_costs rios1_cost = {
COSTS_N_INSNS (2), /* dmul */
COSTS_N_INSNS (19), /* sdiv */
COSTS_N_INSNS (19), /* ddiv */
32,
1024, /* cache lines */
128,
64, /* l1 cache */
512, /* l2 cache */
0, /* streams */
};
......@@ -366,8 +370,9 @@ struct processor_costs rios2_cost = {
COSTS_N_INSNS (2), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (17), /* ddiv */
32,
1024, /* cache lines */
256,
256, /* l1 cache */
1024, /* l2 cache */
0, /* streams */
};
......@@ -385,7 +390,8 @@ struct processor_costs rs64a_cost = {
COSTS_N_INSNS (31), /* sdiv */
COSTS_N_INSNS (31), /* ddiv */
128,
1024, /* cache lines */
128, /* l1 cache */
2048, /* l2 cache */
1, /* streams */
};
......@@ -402,8 +408,9 @@ struct processor_costs mpccore_cost = {
COSTS_N_INSNS (5), /* dmul */
COSTS_N_INSNS (10), /* sdiv */
COSTS_N_INSNS (17), /* ddiv */
128,
512, /* cache lines */
32,
4, /* l1 cache */
16, /* l2 cache */
1, /* streams */
};
......@@ -421,7 +428,8 @@ struct processor_costs ppc403_cost = {
COSTS_N_INSNS (11), /* sdiv */
COSTS_N_INSNS (11), /* ddiv */
32,
128, /* cache lines */
4, /* l1 cache */
16, /* l2 cache */
1, /* streams */
};
......@@ -439,7 +447,8 @@ struct processor_costs ppc405_cost = {
COSTS_N_INSNS (11), /* sdiv */
COSTS_N_INSNS (11), /* ddiv */
32,
512, /* cache lines */
16, /* l1 cache */
128, /* l2 cache */
1, /* streams */
};
......@@ -457,7 +466,8 @@ struct processor_costs ppc440_cost = {
COSTS_N_INSNS (19), /* sdiv */
COSTS_N_INSNS (33), /* ddiv */
32,
1024, /* cache lines */
32, /* l1 cache */
256, /* l2 cache */
1, /* streams */
};
......@@ -475,7 +485,8 @@ struct processor_costs ppc601_cost = {
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (31), /* ddiv */
32,
1024, /* cache lines */
32, /* l1 cache */
256, /* l2 cache */
1, /* streams */
};
......@@ -493,7 +504,8 @@ struct processor_costs ppc603_cost = {
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (33), /* ddiv */
32,
256, /* cache lines */
8, /* l1 cache */
64, /* l2 cache */
1, /* streams */
};
......@@ -511,7 +523,8 @@ struct processor_costs ppc604_cost = {
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (32), /* ddiv */
32,
512, /* cache lines */
16, /* l1 cache */
512, /* l2 cache */
1, /* streams */
};
......@@ -529,7 +542,8 @@ struct processor_costs ppc604e_cost = {
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (32), /* ddiv */
32,
1024, /* cache lines */
32, /* l1 cache */
1024, /* l2 cache */
1, /* streams */
};
......@@ -547,7 +561,8 @@ struct processor_costs ppc620_cost = {
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (32), /* ddiv */
128,
512, /* cache lines */
32, /* l1 cache */
1024, /* l2 cache */
1, /* streams */
};
......@@ -565,7 +580,8 @@ struct processor_costs ppc630_cost = {
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (21), /* ddiv */
128,
512, /* cache lines */
64, /* l1 cache */
1024, /* l2 cache */
1, /* streams */
};
......@@ -584,8 +600,9 @@ struct processor_costs ppccell_cost = {
COSTS_N_INSNS (74/2), /* sdiv */
COSTS_N_INSNS (74/2), /* ddiv */
128,
256, /* cache lines */
6, /* streams */
32, /* l1 cache */
512, /* l2 cache */
6, /* streams */
};
/* Instruction costs on PPC750 and PPC7400 processors. */
......@@ -602,7 +619,8 @@ struct processor_costs ppc750_cost = {
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (31), /* ddiv */
32,
1024, /* cache lines */
32, /* l1 cache */
512, /* l2 cache */
1, /* streams */
};
......@@ -620,7 +638,8 @@ struct processor_costs ppc7450_cost = {
COSTS_N_INSNS (21), /* sdiv */
COSTS_N_INSNS (35), /* ddiv */
32,
1024, /* cache lines */
32, /* l1 cache */
1024, /* l2 cache */
1, /* streams */
};
......@@ -638,7 +657,8 @@ struct processor_costs ppc8540_cost = {
COSTS_N_INSNS (29), /* sdiv */
COSTS_N_INSNS (29), /* ddiv */
32,
1024, /* cache lines */
32, /* l1 cache */
256, /* l2 cache */
1, /* prefetch streams /*/
};
......@@ -656,7 +676,8 @@ struct processor_costs power4_cost = {
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (17), /* ddiv */
128,
256, /* cache lines */
32, /* l1 cache */
1024, /* l2 cache */
8, /* prefetch streams /*/
};
......@@ -674,7 +695,8 @@ struct processor_costs power6_cost = {
COSTS_N_INSNS (13), /* sdiv */
COSTS_N_INSNS (16), /* ddiv */
128,
512, /* cache lines */
64, /* l1 cache */
2048, /* l2 cache */
16, /* prefetch streams */
};
......@@ -1799,9 +1821,11 @@ rs6000_override_options (const char *default_cpu)
set_param_value ("simultaneous-prefetches",
rs6000_cost->simultaneous_prefetches);
if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
set_param_value ("l1-cache-size", rs6000_cost->l1_cache_lines);
set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
}
/* Implement targetm.vectorize.builtin_mask_for_load. */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment