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riscv-gcc-1
Commit 5f6fa212 by Kaz Kojima Committed by Joern Rennecke
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sh.md (udivsi3_i4, [...]): Clobber T register. 

	* gcc/config/sh/sh.md (udivsi3_i4, udivsi3_i4_single): Clobber
	T register.

From-SVN: r37800
parent 8bb9536a
Showing with 7 additions and 0 deletions
gcc/ChangeLog
Mon Nov 27 17:29:44 2000 kaz Kojima <kkojima@rr.iij4u.or.jp>
* gcc/config/sh/sh.md (udivsi3_i4, udivsi3_i4_single): Clobber
T register.
2000-11-27 Richard Earnshaw <rearnsha@arm.com>
* arm.c (select_dominance_cc_mode): Handle new way that combine
......
gcc/config/sh/sh.md
......@@ -980,6 +980,7 @@
(define_insn "udivsi3_i4"
[(set (match_operand:SI 0 "register_operand" "=y")
(udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
(clobber (reg:SI T_REG))
(clobber (reg:SI PR_REG))
(clobber (reg:DF DR0_REG))
(clobber (reg:DF DR2_REG))
......@@ -999,6 +1000,7 @@
(define_insn "udivsi3_i4_single"
[(set (match_operand:SI 0 "register_operand" "=y")
(udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
(clobber (reg:SI T_REG))
(clobber (reg:SI PR_REG))
(clobber (reg:DF DR0_REG))
(clobber (reg:DF DR2_REG))
......
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