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riscv-gcc-1
Commit 5f1e6755 by Nick Clifton
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Rename -mshort-load-bytes switch to -malignment-traps 

From-SVN: r30604
parent 5b8ad699
Showing with 82 additions and 53 deletions
gcc/ChangeLog
Fro Nov 19 05:48:45 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
1999-11-21 Nick Clifton <nickc@cygnus.com>
* invoke.texi (ARM Options): Replace -mshort-load-bytes with
-malignment-traps.
(arm.h): Replace -mshort-load-bytes with -malignment-traps.
(arm.c): Replace TARGET_SHORT_BY_BYTES with TARGET_MMU_TRAPS.
(arm.md): Replace TARGET_SHORT_BY_BYTES with TARGET_MMU_TRAPS.
Sun Nov 21 17:11:13 1999 Geoffrey Keating <geoffk@cygnus.com>
* varasm.c (output_constructor): Solve problem with long long
bitfields, even on BYTES_BIG_ENDIAN machines (testcase 991118-1).
Fri Nov 19 05:48:45 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
* global.c (allocno): New structure and static variable.
(allocno_reg): Remove, all references replaced by allocno.
......@@ -25,11 +38,6 @@ Fro Nov 19 05:48:45 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
pass rtl_dump_file to regclass.
* rtl.h (regclass): Update prototype.
Sun Nov 21 17:11:13 1999 Geoffrey Keating <geoffk@cygnus.com>
* varasm.c (output_constructor): Solve problem with long long
bitfields, even on BYTES_BIG_ENDIAN machines (testcase 991118-1).
Fri Nov 19 06:32:19 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
* i386.md (neg, not and abs patterns): Revmap to use
......
gcc/config/arm/arm.c
......@@ -3483,7 +3483,7 @@ gen_rotated_half_load (memref)
}
/* If we aren't allowed to generate unaligned addresses, then fail. */
if (TARGET_SHORT_BY_BYTES
if (TARGET_MMU_TRAPS
&& ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
return NULL;
......
gcc/config/arm/arm.h
......@@ -285,9 +285,9 @@ Unrecognized value in TARGET_CPU_DEFAULT.
This is equivalent to -fpic. */
#define ARM_FLAG_APCS_REENT (1 << 6)
/* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
loaded byte-at-a-time. */
#define ARM_FLAG_SHORT_BYTE (1 << 7)
/* Nonzero if the MMU will trap unaligned word accesses, so shorts must
be loaded using either LDRH or LDRB instructions. */
#define ARM_FLAG_MMU_TRAPS (1 << 7)
/* Nonzero if all floating point instructions are missing (and there is no
emulator either). Generate function calls for all ops in this case. */
......@@ -323,14 +323,7 @@ Unrecognized value in TARGET_CPU_DEFAULT.
#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
/* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
that short values should not be accessed using word load instructions
as there is a possibility that they may not be word aligned and this
would generate an MMU fault. On processors which do not have a 16 bit
load instruction therefore, short values must be loaded by individual
byte accesses rather than loading a word and then shifting the desired
value into place. */
#define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
#define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
#define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
......@@ -369,12 +362,13 @@ Unrecognized value in TARGET_CPU_DEFAULT.
{"apcs-reentrant", ARM_FLAG_APCS_REENT, \
"Generate re-entrant, PIC code" }, \
{"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
{"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
"Load shorts a byte at a time" }, \
{"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
{"short-load-words", -ARM_FLAG_SHORT_BYTE, \
"Load words a byte at a time" }, \
{"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
{"alignment-traps", ARM_FLAG_MMU_TRAPS, \
"The MMU will trap on unaligned accesses" },\
{"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
{"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
{"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
{"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
{"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
{"soft-float", ARM_FLAG_SOFT_FLOAT, \
"Use library calls to perform FP operations" }, \
{"hard-float", -ARM_FLAG_SOFT_FLOAT, \
......@@ -540,7 +534,7 @@ extern int arm_is_6_or_7;
if (MODE == QImode) \
UNSIGNEDP = 1; \
else if (MODE == HImode) \
UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
(MODE) = SImode; \
}
......@@ -1002,7 +996,7 @@ enum reg_class
/* If we need to load shorts byte-at-a-time, then we need a scratch. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
(((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
(((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
&& (GET_CODE (X) == MEM \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
&& true_regnum (X) == -1))) \
......
gcc/config/arm/arm.md
......@@ -2441,7 +2441,7 @@
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
{
/* Note: We do not have to worry about TARGET_SHORT_BY_BYTES
/* Note: We do not have to worry about TARGET_MMU_TRAPS
here because the insn below will generate an LDRH instruction
rather than an LDR instruction, so we cannot get an unaligned
word access. */
......@@ -2449,7 +2449,7 @@
gen_rtx_ZERO_EXTEND (SImode, operands[1])));
DONE;
}
if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
if (TARGET_MMU_TRAPS && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_movhi_bytes (operands[0], operands[1]));
DONE;
......@@ -2549,7 +2549,7 @@
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
{
/* Note: We do not have to worry about TARGET_SHORT_BY_BYTES
/* Note: We do not have to worry about TARGET_MMU_TRAPS
here because the insn below will generate an LDRH instruction
rather than an LDR instruction, so we cannot get an unaligned
word access. */
......@@ -2558,7 +2558,7 @@
DONE;
}
if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
if (TARGET_MMU_TRAPS && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
DONE;
......@@ -3184,13 +3184,13 @@
}
else if (! arm_arch4)
{
/* Note: We do not have to worry about TARGET_SHORT_BY_BYTES
/* Note: We do not have to worry about TARGET_MMU_TRAPS
for v4 and up architectures because LDRH instructions will
be used to access the HI values, and these cannot generate
unaligned word access faults in the MMU. */
if (GET_CODE (operands[1]) == MEM)
{
if (TARGET_SHORT_BY_BYTES)
if (TARGET_MMU_TRAPS)
{
rtx base;
rtx offset = const0_rtx;
......@@ -3289,7 +3289,7 @@
[(set (match_operand:SI 0 "s_register_operand" "=r")
(rotate:SI (match_operand:SI 1 "offsettable_memory_operand" "o")
(const_int 16)))]
"! TARGET_SHORT_BY_BYTES"
"! TARGET_MMU_TRAPS"
"*
{
rtx ops[2];
......@@ -3373,7 +3373,7 @@
(match_operand:HI 1 "general_operand" "rI,K,m"))]
"! arm_arch4
&& ! BYTES_BIG_ENDIAN
&& ! TARGET_SHORT_BY_BYTES
&& ! TARGET_MMU_TRAPS
&& (GET_CODE (operands[1]) != CONST_INT
|| const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1])))"
......@@ -3389,7 +3389,7 @@
(match_operand:HI 1 "general_operand" "rI,K,m"))]
"! arm_arch4
&& BYTES_BIG_ENDIAN
&& ! TARGET_SHORT_BY_BYTES
&& ! TARGET_MMU_TRAPS
&& (GET_CODE (operands[1]) != CONST_INT
|| const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1])))"
......@@ -3406,7 +3406,7 @@
(rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "m") 0)
(const_int 16)))]
"BYTES_BIG_ENDIAN
&& ! TARGET_SHORT_BY_BYTES"
&& ! TARGET_MMU_TRAPS"
"ldr%?\\t%0, %1\\t%@ movhi_bigend"
[(set_attr "type" "load")
(set_attr "pool_range" "4096")])
......@@ -3414,7 +3414,7 @@
(define_insn "*movhi_bytes"
[(set (match_operand:HI 0 "s_register_operand" "=r,r")
(match_operand:HI 1 "arm_rhs_operand" "rI,K"))]
"TARGET_SHORT_BY_BYTES"
"TARGET_MMU_TRAPS"
"@
mov%?\\t%0, %1\\t%@ movhi
mvn%?\\t%0, #%B1\\t%@ movhi")
......@@ -3436,7 +3436,7 @@
[(parallel [(match_operand:HI 0 "s_register_operand" "=r")
(match_operand:HI 1 "reload_memory_operand" "o")
(match_operand:DI 2 "s_register_operand" "=&r")])]
"TARGET_SHORT_BY_BYTES"
"TARGET_MMU_TRAPS"
"
arm_reload_in_hi (operands);
DONE;
......@@ -5932,7 +5932,7 @@
(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (match_dup 1) (match_dup 2)))]
"(! BYTES_BIG_ENDIAN)
&& ! TARGET_SHORT_BY_BYTES
&& ! TARGET_MMU_TRAPS
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& (GET_CODE (operands[2]) != REG
......@@ -5947,7 +5947,7 @@
(set (match_operand:SI 0 "s_register_operand" "=r")
(minus:SI (match_dup 1) (match_dup 2)))]
"(!BYTES_BIG_ENDIAN)
&& ! TARGET_SHORT_BY_BYTES
&& ! TARGET_MMU_TRAPS
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& (GET_CODE (operands[2]) != REG
......@@ -6085,7 +6085,7 @@
(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
(match_dup 1)))]
"(! BYTES_BIG_ENDIAN)
&& ! TARGET_SHORT_BY_BYTES
&& ! TARGET_MMU_TRAPS
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
......@@ -6102,7 +6102,7 @@
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
(match_dup 4)])))]
"(! BYTES_BIG_ENDIAN)
&& ! TARGET_SHORT_BY_BYTES
&& ! TARGET_MMU_TRAPS
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
......@@ -6149,7 +6149,7 @@
(set (match_dup 1)
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
"(! BYTES_BIG_ENDIAN)
&& ! TARGET_SHORT_BY_BYTES
&& ! TARGET_MMU_TRAPS
&& REGNO(operands[0]) != REGNO(operands[1])
&& (GET_CODE (operands[2]) != REG
|| REGNO(operands[0]) != REGNO (operands[2]))"
......
gcc/invoke.texi
......@@ -261,7 +261,7 @@ in the following sections.
-mapcs-reentrant -mno-apcs-reentrant
-msched-prolog -mno-sched-prolog
-mlittle-endian -mbig-endian -mwords-little-endian
-mshort-load-bytes -mno-short-load-bytes -mshort-load-words -mno-short-load-words
-malignment-traps
-msoft-float -mhard-float -mfpe
-mthumb-interwork -mno-thumb-interwork
-mcpu= -march= -mfpe=
......@@ -4372,26 +4372,53 @@ option should only be used if you require compatibility with code for
big-endian ARM processors generated by versions of the compiler prior to
2.8.
@item -malignment-traps
@kindex -malignment-traps
Generate code that will not trap if the MMU has alignment traps enabled.
On ARM architectures prior to ARMv4, there were no instructions to
access half-word objects stored in memory. However, when reading from
memory a feature of the ARM architecture allows a word load to be used,
even if the address is unaligned, and the processor core will rotate the
data as it is being loaded. This option tells the compiler that such
misaligned accesses will cause a MMU trap and that it should instead
synthesise the access as a series of byte accesses. The compiler can
still use word accesses to load half-word data if it knows that the
address is aligned to a word boundary.
This option is ignored when compiling for ARM architecture 4 or later,
since these processors have instructions to directly access half-word
objects in memory.
@item -mno-alignment-traps
@kindex -mno-alignment-traps
Generate code that assumes that the MMU will not trap unaligned
accesses. This produces better code when the target instruction set
does not have half-word memory operations (implementations prior to
ARMv4).
Note that you cannot use this option to access unaligned word objects,
since the processor will only fetch one 32-bit aligned object from
memory.
The default setting for most targets is -mno-alignment-traps, since
this produces better code when there are no half-word memory
instructions available.
@item -mshort-load-bytes
@kindex -mshort-load-bytes
Do not try to load half-words (eg @samp{short}s) by loading a word from
an unaligned address. For some targets the MMU is configured to trap
unaligned loads; use this option to generate code that is safe in these
environments.
This is a depreciated alias for @samp{-malignment-traps}.
@item -mno-short-load-bytes
@kindex -mno-short-load-bytes
Use unaligned word loads to load half-words (eg @samp{short}s). This
option produces more efficient code, but the MMU is sometimes configured
to trap these instructions.
This is a depreciated alias for @samp{-mno-alignment-traps}.
@item -mshort-load-words
@kindex -mshort-load-words
This is a synonym for @samp{-mno-short-load-bytes}.
This is a depreciated alias for @samp{-mno-alignment-traps}.
@item -mno-short-load-words
@kindex -mno-short-load-words
This is a synonym for @samp{-mshort-load-bytes}.
This is a depreciated alias for @samp{-malignment-traps}.
@item -mbsd
@kindex -mbsd
......
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