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Commit 5e7d8b4c by Richard Sandiford
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constraints.md: Add new register constraint "kb". 

gcc/
2014-04-12  Catherine Moore  <clm@codesourcery.com>

	* config/mips/constraints.md: Add new register constraint "kb".
	* config/mips/mips.md (*mov<mode>_internal): Use constraint "kb".
	(*movhi_internal): Likewise.
	(*movqi_internal): Likewise.
	* config/mips/mips.h (M16_STORE_REGS): New register class.
	(REG_CLASS_NAMES): Add M16_STORE_REGS.
	(REG_CLASS_CONTENTS): Likewise.
	* config/mips/mips.c (mips_regno_to_class): Add M16_STORE_REGS.

gcc/testsuite/
	* gcc.target/mips/umips-store16-1.c: New test.

From-SVN: r209334
parent 09b1b833
Showing with 63 additions and 11 deletions
gcc/ChangeLog
2014-04-12 Catherine Moore <clm@codesourcery.com>
* config/mips/constraints.md: Add new register constraint "kb".
* config/mips/mips.md (*mov<mode>_internal): Use constraint "kb".
(*movhi_internal): Likewise.
(*movqi_internal): Likewise.
* config/mips/mips.h (M16_STORE_REGS): New register class.
(REG_CLASS_NAMES): Add M16_STORE_REGS.
(REG_CLASS_CONTENTS): Likewise.
* config/mips/mips.c (mips_regno_to_class): Add M16_STORE_REGS.
2014-04-11 Tobias Burnus <burnus@net-b.de>
PR c/60194
......
gcc/config/mips/constraints.md
......@@ -92,6 +92,9 @@
;; but the DSP version allows any accumulator target.
(define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS")
(define_register_constraint "kb" "M16_STORE_REGS"
"@internal")
(define_constraint "kf"
"@internal"
(match_operand 0 "force_to_mem_operand"))
......
gcc/config/mips/mips.c
......@@ -648,14 +648,15 @@ static mips_one_only_stub *mips16_set_fcsr_stub;
/* Index R is the smallest register class that contains register R. */
const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
M16_REGS, M16_REGS, M16_REGS, M16_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG,
M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
......
gcc/config/mips/mips.h
......@@ -1870,6 +1870,7 @@ struct mips_cpu_info {
enum reg_class
{
NO_REGS, /* no registers in set */
M16_STORE_REGS, /* microMIPS store registers */
M16_REGS, /* mips16 directly accessible registers */
T_REG, /* mips16 T register ($24) */
M16_T_REGS, /* mips16 registers plus T register */
......@@ -1907,6 +1908,7 @@ enum reg_class
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"M16_STORE_REGS", \
"M16_REGS", \
"T_REG", \
"M16_T_REGS", \
......@@ -1947,6 +1949,7 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
{ 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
......
gcc/config/mips/mips.md
......@@ -4437,7 +4437,7 @@
(define_insn "*mov<mode>_internal"
[(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
(match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!u,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
(match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!kb,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], <MODE>mode)
|| reg_or_0_operand (operands[1], <MODE>mode))"
......@@ -4578,7 +4578,7 @@
(define_insn "*movhi_internal"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d")
(match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!u,dJ,*d*J,*a"))]
(match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!kb,dJ,*d*J,*a"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))"
......@@ -4654,7 +4654,7 @@
(define_insn "*movqi_internal"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d")
(match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!u,dJ,*d*J,*a"))]
(match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!kb,dJ,*d*J,*a"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))"
......
gcc/testsuite/ChangeLog
2014-04-12 Richard Sandiford <rdsandiford@googlemail.com>
* gcc.target/mips/umips-store16-1.c: New test.
2014-04-11 Tobias Burnus <burnus@net-b.de>
PR c/60194
......
gcc/testsuite/gcc.target/mips/umips-store16-1.c 0 → 100644
/* { dg-options "(-mmicromips)" } */
/* { dg-do assemble } */
register unsigned int global asm ("$16");
extern void exit (int) __attribute__((noreturn));
MICROMIPS void
test_sb (unsigned char *ptr, void (*f) (void))
{
ptr[0] = global;
f ();
exit (0);
}
MICROMIPS void
test_sh (unsigned short *ptr, void (*f) (void))
{
ptr[0] = global;
f ();
exit (0);
}
MICROMIPS void
test_sw (unsigned int *ptr, void (*f) (void))
{
ptr[0] = global;
f ();
exit (0);
}
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