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riscv-gcc-1
Commit 5d4f5e87 by Doug Evans
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sparc.md (*): Use GEN_INT instead of gen_rtx. 

	* sparc/sparc.md (*): Use GEN_INT instead of gen_rtx.
	(get_pc_sp32): Use for sparc64 as well.
	(lo_sum_di_sp{32,64}): Fix handling on 64 bit hosts.
	(sethi_di_sp64_const): Likewise.
	(movtf_cc_sp64): Check TARGET_HARD_QUAD.
	(cmp_zero_extract_sp64): Use unsigned HOST_WIDE_INT in cast.
	(ashlsi3, ashldi3, ashrsi3, ashrdi3, lshrsi3, lshrdi3): Likewise.

From-SVN: r15705
parent 26b551af
Showing with 63 additions and 33 deletions
gcc/config/sparc/sparc.md
...@@ -1533,14 +1533,14 @@ ...@@ -1533,14 +1533,14 @@
[(set_attr "type" "move") [(set_attr "type" "move")
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "get_pc_sp32" (define_insn "get_pc_via_call"
[(set (pc) (label_ref (match_operand 0 "" ""))) [(set (pc) (label_ref (match_operand 0 "" "")))
(set (reg:SI 15) (label_ref (match_dup 0)))] (set (reg:SI 15) (label_ref (match_operand 1 "" "")))]
"! TARGET_PTR64" ""
"call %l0%#" "call %l0%#"
[(set_attr "type" "uncond_branch")]) [(set_attr "type" "uncond_branch")])
(define_insn "get_pc_sp64" (define_insn "get_pc_via_rdpc"
[(set (match_operand:DI 0 "register_operand" "=r") (pc))] [(set (match_operand:DI 0 "register_operand" "=r") (pc))]
"TARGET_PTR64" "TARGET_PTR64"
"rd %%pc,%0" "rd %%pc,%0"
...@@ -1611,7 +1611,12 @@ ...@@ -1611,7 +1611,12 @@
/* Don't output a 64 bit constant, since we can't trust the assembler to /* Don't output a 64 bit constant, since we can't trust the assembler to
handle it correctly. */ handle it correctly. */
if (GET_CODE (operands[2]) == CONST_DOUBLE) if (GET_CODE (operands[2]) == CONST_DOUBLE)
operands[2] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[2])); operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
else if (GET_CODE (operands[2]) == CONST_INT
&& HOST_BITS_PER_WIDE_INT > 32
&& INTVAL (operands[2]) > 0xffffffff)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
return \"or %L1,%%lo(%a2),%L0\"; return \"or %L1,%%lo(%a2),%L0\";
}" }"
;; Need to set length for this arith insn because operand2 ;; Need to set length for this arith insn because operand2
...@@ -1630,7 +1635,12 @@ ...@@ -1630,7 +1635,12 @@
/* Don't output a 64 bit constant, since we can't trust the assembler to /* Don't output a 64 bit constant, since we can't trust the assembler to
handle it correctly. */ handle it correctly. */
if (GET_CODE (operands[2]) == CONST_DOUBLE) if (GET_CODE (operands[2]) == CONST_DOUBLE)
operands[2] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[2])); operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
else if (GET_CODE (operands[2]) == CONST_INT
&& HOST_BITS_PER_WIDE_INT > 32
&& INTVAL (operands[2]) > 0xffffffff)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
/* Note that we use add here. This is important because Medium/Anywhere /* Note that we use add here. This is important because Medium/Anywhere
code model support depends on it. */ code model support depends on it. */
return \"add %1,%%lo(%a2),%0\"; return \"add %1,%%lo(%a2),%0\";
...@@ -1662,11 +1672,11 @@ ...@@ -1662,11 +1672,11 @@
else if (GET_CODE (op1) == CONST_DOUBLE) else if (GET_CODE (op1) == CONST_DOUBLE)
{ {
operands[0] = operand_subword (op0, 1, 0, DImode); operands[0] = operand_subword (op0, 1, 0, DImode);
operands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (op1)); operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
output_asm_insn (\"sethi %%hi(%a1),%0\", operands); output_asm_insn (\"sethi %%hi(%a1),%0\", operands);
operands[0] = operand_subword (op0, 0, 0, DImode); operands[0] = operand_subword (op0, 0, 0, DImode);
operands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (op1)); operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
return singlemove_string (operands); return singlemove_string (operands);
} }
else else
...@@ -1700,6 +1710,7 @@ ...@@ -1700,6 +1710,7 @@
"TARGET_ARCH64 && check_pic (1)" "TARGET_ARCH64 && check_pic (1)"
"* "*
{ {
#if HOST_BITS_PER_WIDE_INT == 32
rtx high, low; rtx high, low;
split_double (operands[1], &high, &low); split_double (operands[1], &high, &low);
...@@ -1719,6 +1730,26 @@ ...@@ -1719,6 +1730,26 @@
if (low != const0_rtx) if (low != const0_rtx)
output_asm_insn (\"sethi %%hi(%a1),%%g1; or %0,%%g1,%0\", operands); output_asm_insn (\"sethi %%hi(%a1),%%g1; or %0,%%g1,%0\", operands);
} }
#else
rtx op = operands[1];
if (! SPARC_SETHI_P (INTVAL(op)))
{
operands[1] = GEN_INT (INTVAL (op) >> 32);
output_asm_insn (singlemove_string (operands), operands);
output_asm_insn (\"sllx %0,32,%0\", operands);
if (INTVAL (op) & 0xffffffff)
{
operands[1] = GEN_INT (INTVAL (op) & 0xffffffff);
output_asm_insn (\"sethi %%hi(%a1),%%g1; or %0,%%g1,%0\", operands);
}
}
else
{
output_asm_insn (\"sethi %%hi(%a1),%0\", operands);
}
#endif
return \"\"; return \"\";
}" }"
...@@ -2030,8 +2061,7 @@ ...@@ -2030,8 +2061,7 @@
return \"sethi %%hi(%a1),%0\"; return \"sethi %%hi(%a1),%0\";
else else
{ {
operands[1] = gen_rtx (CONST_INT, VOIDmode, operands[1] = GEN_INT (~INTVAL (operands[1]));
~ INTVAL (operands[1]));
output_asm_insn (\"sethi %%hi(%a1),%0\", operands); output_asm_insn (\"sethi %%hi(%a1),%0\", operands);
/* The low 10 bits are already zero, but invert the rest. /* The low 10 bits are already zero, but invert the rest.
Assemblers don't accept 0x1c00, so use -0x400 instead. */ Assemblers don't accept 0x1c00, so use -0x400 instead. */
...@@ -2698,7 +2728,7 @@ ...@@ -2698,7 +2728,7 @@
(const_int 0)]) (const_int 0)])
(match_operand:TF 3 "register_operand" "e,0") (match_operand:TF 3 "register_operand" "e,0")
(match_operand:TF 4 "register_operand" "0,e")))] (match_operand:TF 4 "register_operand" "0,e")))]
"TARGET_V9 && TARGET_FPU" "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
"@ "@
fmovq%C1 %x2,%3,%0 fmovq%C1 %x2,%3,%0
fmovq%c1 %x2,%4,%0" fmovq%c1 %x2,%4,%0"
...@@ -2809,7 +2839,7 @@ ...@@ -2809,7 +2839,7 @@
" "
{ {
rtx temp = gen_reg_rtx (SImode); rtx temp = gen_reg_rtx (SImode);
rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); rtx shift_16 = GEN_INT (16);
int op1_subword = 0; int op1_subword = 0;
if (GET_CODE (operand1) == SUBREG) if (GET_CODE (operand1) == SUBREG)
...@@ -2887,7 +2917,7 @@ ...@@ -2887,7 +2917,7 @@
" "
{ {
rtx temp = gen_reg_rtx (DImode); rtx temp = gen_reg_rtx (DImode);
rtx shift_48 = gen_rtx (CONST_INT, VOIDmode, 48); rtx shift_48 = GEN_INT (48);
int op1_subword = 0; int op1_subword = 0;
if (GET_CODE (operand1) == SUBREG) if (GET_CODE (operand1) == SUBREG)
...@@ -2981,7 +3011,7 @@ ...@@ -2981,7 +3011,7 @@
" "
{ {
rtx temp = gen_reg_rtx (SImode); rtx temp = gen_reg_rtx (SImode);
rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); rtx shift_16 = GEN_INT (16);
int op1_subword = 0; int op1_subword = 0;
if (GET_CODE (operand1) == SUBREG) if (GET_CODE (operand1) == SUBREG)
...@@ -3011,7 +3041,7 @@ ...@@ -3011,7 +3041,7 @@
" "
{ {
rtx temp = gen_reg_rtx (SImode); rtx temp = gen_reg_rtx (SImode);
rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); rtx shift_24 = GEN_INT (24);
int op1_subword = 0; int op1_subword = 0;
int op0_subword = 0; int op0_subword = 0;
...@@ -3048,7 +3078,7 @@ ...@@ -3048,7 +3078,7 @@
" "
{ {
rtx temp = gen_reg_rtx (SImode); rtx temp = gen_reg_rtx (SImode);
rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); rtx shift_24 = GEN_INT (24);
int op1_subword = 0; int op1_subword = 0;
if (GET_CODE (operand1) == SUBREG) if (GET_CODE (operand1) == SUBREG)
...@@ -3078,7 +3108,7 @@ ...@@ -3078,7 +3108,7 @@
" "
{ {
rtx temp = gen_reg_rtx (DImode); rtx temp = gen_reg_rtx (DImode);
rtx shift_56 = gen_rtx (CONST_INT, VOIDmode, 56); rtx shift_56 = GEN_INT (56);
int op1_subword = 0; int op1_subword = 0;
if (GET_CODE (operand1) == SUBREG) if (GET_CODE (operand1) == SUBREG)
...@@ -3108,7 +3138,7 @@ ...@@ -3108,7 +3138,7 @@
" "
{ {
rtx temp = gen_reg_rtx (DImode); rtx temp = gen_reg_rtx (DImode);
rtx shift_48 = gen_rtx (CONST_INT, VOIDmode, 48); rtx shift_48 = GEN_INT (48);
int op1_subword = 0; int op1_subword = 0;
if (GET_CODE (operand1) == SUBREG) if (GET_CODE (operand1) == SUBREG)
...@@ -3164,7 +3194,7 @@ ...@@ -3164,7 +3194,7 @@
int pos = 32 - INTVAL (operands[2]) - len; int pos = 32 - INTVAL (operands[2]) - len;
unsigned mask = ((1 << len) - 1) << pos; unsigned mask = ((1 << len) - 1) << pos;
operands[1] = gen_rtx (CONST_INT, VOIDmode, mask); operands[1] = GEN_INT (mask);
return \"andcc %0,%1,%%g0\"; return \"andcc %0,%1,%%g0\";
}") }")
...@@ -3180,9 +3210,9 @@ ...@@ -3180,9 +3210,9 @@
{ {
int len = INTVAL (operands[1]); int len = INTVAL (operands[1]);
int pos = 64 - INTVAL (operands[2]) - len; int pos = 64 - INTVAL (operands[2]) - len;
unsigned mask = ((1 << len) - 1) << pos; unsigned HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
operands[1] = gen_rtx (CONST_INT, VOIDmode, mask); operands[1] = GEN_INT (mask);
return \"andcc %0,%1,%%g0\"; return \"andcc %0,%1,%%g0\";
}") }")
...@@ -4100,7 +4130,7 @@ ...@@ -4100,7 +4130,7 @@
(set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))] (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
" "
{ {
operands[4] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2])); operands[4] = GEN_INT (~INTVAL (operands[2]));
}") }")
(define_insn "*and_not_di_sp32" (define_insn "*and_not_di_sp32"
...@@ -4186,7 +4216,7 @@ ...@@ -4186,7 +4216,7 @@
(set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))] (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
" "
{ {
operands[4] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2])); operands[4] = GEN_INT (~INTVAL (operands[2]));
}") }")
(define_insn "*or_not_di_sp32" (define_insn "*or_not_di_sp32"
...@@ -4272,7 +4302,7 @@ ...@@ -4272,7 +4302,7 @@
(set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))] (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
" "
{ {
operands[4] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2])); operands[4] = GEN_INT (~INTVAL (operands[2]));
}") }")
(define_split (define_split
...@@ -4287,7 +4317,7 @@ ...@@ -4287,7 +4317,7 @@
(set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))] (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
" "
{ {
operands[4] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2])); operands[4] = GEN_INT (~INTVAL (operands[2]));
}") }")
;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b). ;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).
...@@ -4855,7 +4885,7 @@ ...@@ -4855,7 +4885,7 @@
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) INTVAL (operands[2]) > 31) && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return \"sll %1,%2,%0\"; return \"sll %1,%2,%0\";
...@@ -4870,7 +4900,7 @@ ...@@ -4870,7 +4900,7 @@
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) INTVAL (operands[2]) > 63) && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return \"sllx %1,%2,%0\"; return \"sllx %1,%2,%0\";
...@@ -4903,7 +4933,7 @@ ...@@ -4903,7 +4933,7 @@
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) INTVAL (operands[2]) > 31) && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return \"sra %1,%2,%0\"; return \"sra %1,%2,%0\";
...@@ -4918,7 +4948,7 @@ ...@@ -4918,7 +4948,7 @@
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) INTVAL (operands[2]) > 63) && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return \"srax %1,%2,%0\"; return \"srax %1,%2,%0\";
...@@ -4932,7 +4962,7 @@ ...@@ -4932,7 +4962,7 @@
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) INTVAL (operands[2]) > 31) && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return \"srl %1,%2,%0\"; return \"srl %1,%2,%0\";
...@@ -4947,7 +4977,7 @@ ...@@ -4947,7 +4977,7 @@
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) INTVAL (operands[2]) > 63) && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return \"srlx %1,%2,%0\"; return \"srlx %1,%2,%0\";
...@@ -5075,9 +5105,9 @@ ...@@ -5075,9 +5105,9 @@
means 6 on the sparc. */ means 6 on the sparc. */
#if 0 #if 0
if (operands[2]) if (operands[2])
nregs_rtx = gen_rtx (CONST_INT, VOIDmode, REGNO (operands[2]) - 8); nregs_rtx = GEN_INT (REGNO (operands[2]) - 8);
else else
nregs_rtx = gen_rtx (CONST_INT, VOIDmode, 6); nregs_rtx = GEN_INT (6);
#else #else
nregs_rtx = const0_rtx; nregs_rtx = const0_rtx;
#endif #endif
......
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