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riscv-gcc-1
Commit 5d17176f by Torbjorn Granlund
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(andsi3): Match op2 with logic_operand, change constraint accordingly. 

(andsi3): Match op2 with logic_operand, change constraint
accordingly.  Output andnot for negative op2.
(iorsi3, xorsi3): Analogous changes.
Move all plain logical patterns together.

From-SVN: r10724
parent fb3ba99d
Showing with 87 additions and 77 deletions
gcc/config/i960/i960.md
...@@ -1645,11 +1645,13 @@ ...@@ -1645,11 +1645,13 @@
(define_insn "andsi3" (define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (match_operand:SI 1 "arith_operand" "%dI") (and:SI (match_operand:SI 1 "register_operand" "%d")
(match_operand:SI 2 "arith_operand" "dI")))] (match_operand:SI 2 "logic_operand" "dIM")))]
"" ""
"* "*
{ {
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
return \"andnot %C2,%1,%0\";
if (i960_bypass (insn, operands[1], operands[2], 0)) if (i960_bypass (insn, operands[1], operands[2], 0))
return \"and %2,%1,%0\"; return \"and %2,%1,%0\";
return \"and %1,%2,%0\"; return \"and %1,%2,%0\";
...@@ -1657,11 +1659,25 @@ ...@@ -1657,11 +1659,25 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) (and:SI (match_operand:SI 1 "arith_operand" "dI")
(match_operand:SI 2 "arith_operand" "dI")))] (match_operand:SI 2 "cmplpower2_operand" "n")))]
"" ""
"* "*
{ {
operands[2] = gen_rtx (CONST_INT, VOIDmode,
bitpos (~INTVAL (operands[2])));
return \"clrbit %2,%1,%0\";
}")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
(match_operand:SI 2 "logic_operand" "dIM")))]
""
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
return \"nor %C2,%1,%0\";
if (i960_bypass (insn, operands[1], operands[2], 0)) if (i960_bypass (insn, operands[1], operands[2], 0))
return \"notand %2,%1,%0\"; return \"notand %2,%1,%0\";
return \"andnot %1,%2,%0\"; return \"andnot %1,%2,%0\";
...@@ -1669,8 +1685,8 @@ ...@@ -1669,8 +1685,8 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(ior:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) (ior:SI (not:SI (match_operand:SI 1 "register_operand" "%d"))
(not:SI (match_operand:SI 2 "arith_operand" "dI"))))] (not:SI (match_operand:SI 2 "register_operand" "d"))))]
"" ""
"* "*
{ {
...@@ -1679,9 +1695,23 @@ ...@@ -1679,9 +1695,23 @@
return \"nand %1,%2,%0\"; return \"nand %1,%2,%0\";
}") }")
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(ior:SI (match_operand:SI 1 "register_operand" "%d")
(match_operand:SI 2 "logic_operand" "dIM")))]
""
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
return \"ornot %C2,%1,%0\";
if (i960_bypass (insn, operands[1], operands[2], 0))
return \"or %2,%1,%0\";
return \"or %1,%2,%0\";
}")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(ior:SI (match_operand:SI 1 "arith_operand" "dI") (ior:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "power2_operand" "n")))] (match_operand:SI 2 "power2_operand" "n")))]
"" ""
"* "*
...@@ -1693,42 +1723,43 @@ ...@@ -1693,42 +1723,43 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(ior:SI (ashift:SI (const_int 1) (ior:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
(match_operand:SI 1 "register_operand" "d")) (match_operand:SI 2 "logic_operand" "dIM")))]
(match_operand:SI 2 "arith_operand" "dI")))]
"" ""
"setbit %1,%2,%0") "*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
return \"nand %C2,%1,%0\";
if (i960_bypass (insn, operands[1], operands[2], 0))
return \"notor %2,%1,%0\";
return \"ornot %1,%2,%0\";
}")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (match_operand:SI 1 "arith_operand" "dI") (and:SI (not:SI (match_operand:SI 1 "register_operand" "%d"))
(match_operand:SI 2 "cmplpower2_operand" "n")))] (not:SI (match_operand:SI 2 "register_operand" "d"))))]
"" ""
"* "*
{ {
operands[2] = gen_rtx (CONST_INT, VOIDmode, if (i960_bypass (insn, operands[1], operands[2], 0))
bitpos (~INTVAL (operands[2]))); return \"nor %2,%1,%0\";
return \"clrbit %2,%1,%0\"; return \"nor %1,%2,%0\";
}") }")
;; (not (ashift 1 reg)) canonicalizes to (rotate -2 reg) (define_insn "xorsi3"
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (rotate:SI (const_int -2) (xor:SI (match_operand:SI 1 "register_operand" "%d")
(match_operand:SI 1 "register_operand" "d")) (match_operand:SI 2 "logic_operand" "dIM")))]
(match_operand:SI 2 "register_operand" "d")))]
""
"clrbit %1,%2,%0")
;; The above pattern canonicalizes to this when both the input and output
;; are the same pseudo-register.
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=d")
(const_int 1)
(match_operand:SI 1 "register_operand" "d"))
(const_int 0))]
"" ""
"clrbit %1,%0,%0") "*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
return \"xnor %C2,%1,%0\";
if (i960_bypass (insn, operands[1], operands[2], 0))
return \"xor %2,%1,%0\";
return \"xor %1,%2,%0\";
}")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
...@@ -1744,71 +1775,50 @@ ...@@ -1744,71 +1775,50 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(xor:SI (ashift:SI (const_int 1) (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%d")
(match_operand:SI 1 "register_operand" "d")) (match_operand:SI 2 "register_operand" "d"))))]
(match_operand:SI 2 "arith_operand" "dI")))]
""
"notbit %1,%2,%0")
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(ior:SI (match_operand:SI 1 "arith_operand" "%dI")
(match_operand:SI 2 "arith_operand" "dI")))]
"" ""
"* "*
{ {
if (i960_bypass (insn, operands[1], operands[2], 0)) if (i960_bypass (insn, operands[1], operands[2], 0))
return \"or %2,%1,%0\"; return \"xnor %2,%1,%0\";
return \"or %1,%2,%0\"; return \"xnor %2,%1,%0\";
}") }")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(ior:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) (ior:SI (ashift:SI (const_int 1)
(match_operand:SI 1 "register_operand" "d"))
(match_operand:SI 2 "arith_operand" "dI")))] (match_operand:SI 2 "arith_operand" "dI")))]
"" ""
"* "setbit %1,%2,%0")
{
if (i960_bypass (insn, operands[1], operands[2], 0))
return \"notor %2,%1,%0\";
return \"ornot %1,%2,%0\";
}")
;; (not (ashift 1 reg)) canonicalizes to (rotate -2 reg)
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) (and:SI (rotate:SI (const_int -2)
(not:SI (match_operand:SI 2 "arith_operand" "dI"))))] (match_operand:SI 1 "register_operand" "d"))
(match_operand:SI 2 "register_operand" "d")))]
"" ""
"* "clrbit %1,%2,%0")
{
if (i960_bypass (insn, operands[1], operands[2], 0))
return \"nor %2,%1,%0\";
return \"nor %1,%2,%0\";
}")
(define_insn "xorsi3" ;; The above pattern canonicalizes to this when both the input and output
[(set (match_operand:SI 0 "register_operand" "=d") ;; are the same pseudo-register.
(xor:SI (match_operand:SI 1 "arith_operand" "%dI") (define_insn ""
(match_operand:SI 2 "arith_operand" "dI")))] [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=d")
(const_int 1)
(match_operand:SI 1 "register_operand" "d"))
(const_int 0))]
"" ""
"* "clrbit %1,%0,%0")
{
if (i960_bypass (insn, operands[1], operands[2], 0))
return \"xor %2,%1,%0\";
return \"xor %1,%2,%0\";
}")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(not:SI (xor:SI (match_operand:SI 1 "arith_operand" "%dI") (xor:SI (ashift:SI (const_int 1)
(match_operand:SI 2 "arith_operand" "dI"))))] (match_operand:SI 1 "register_operand" "d"))
(match_operand:SI 2 "arith_operand" "dI")))]
"" ""
"* "notbit %1,%2,%0")
{
if (i960_bypass (insn, operands[1], operands[2], 0))
return \"xnor %2,%1,%0\";
return \"xnor %2,%1,%0\";
}")
(define_insn "negsi2" (define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
......
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