cortex-a8.md (cortex_a8_load_store_2): Reserve cortex_a8_issue_ls.

	* config/arm/cortex-a8.md (cortex_a8_load_store_2): Reserve
	cortex_a8_issue_ls.

From-SVN: r162201

gcc/ChangeLog

+2010-07-15  Jie Zhang  <jie@codesourcery.com>
+
+	* config/arm/cortex-a8.md (cortex_a8_load_store_2): Reserve
+	cortex_a8_issue_ls.
+
 2010-07-15  Dave Korn  <dave.korn.cygwin@gmail.com>
 
 	* config/i386/cygwin.h (LIBGCJ_SONAME): Update.

gcc/config/arm/cortex-a8.md

@@ -47,17 +47,15 @@
                     "(cortex_a8_alu0+cortex_a8_issue_ls)|\
                      (cortex_a8_alu1+cortex_a8_issue_ls)")
 
-;; ...and in the case of two micro-ops.  We don't need to reserve
-;; cortex_a8_issue_ls here because dual issue is altogether forbidden
+;; ...and in the case of two micro-ops.  Dual issue is altogether forbidden
 ;; during the issue cycle of the first micro-op.  (Instead of modelling
 ;; a separate issue unit, we instead reserve alu0 and alu1 to
 ;; prevent any other instructions from being issued upon that first cycle.)
 ;; Even though the load/store pipeline is usually available in either
-;; ALU pipe, multi-cycle instructions always issue in pipeline 0.  This
-;; reservation is therefore the same as cortex_a8_multiply_2 below.
+;; ALU pipe, multi-cycle instructions always issue in pipeline 0.
 (define_reservation "cortex_a8_load_store_2"
-                    "cortex_a8_alu0+cortex_a8_alu1,\
-                     cortex_a8_alu0")
+                    "cortex_a8_alu0+cortex_a8_alu1+cortex_a8_issue_ls,\
+                     cortex_a8_alu0+cortex_a8_issue_ls")
 
 ;; The flow of a single-cycle multiplication.
 (define_reservation "cortex_a8_multiply"