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riscv-gcc-1
Commit 5cb01b65 by Jakub Jelinek Committed by Richard Henderson
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Jakub Jelinek <jj@ultra.linux.cz> 

        * config/sparc/linux64.h (CC1_SPEC): Preserve CPU specified by
        the user if using the non-default arch size in BI_ARCH configuration.
        * config/sparc/sol2-sld-64.h (CC1_SPEC): Ditto.

        * config/sparc/sparc.md (cmp_mul_set, cmp_udiv_cc_set):
        Fix patterns so that they actually match.
        (cmp_sdiv_cc_set): Ditto, also don't require g0 to be zero.
        (mulsidi3_sp64, const_mulsidi3_sp64): New patterns.
        (const_mulsidi3_sp32): Renamed from const_mulsidi3, only on
        TARGET_HARD_MUL32.
        (mulsidi3): Reflect this in the expand.
        (smulsi3_highpart): Only on TARGET_ARCH32.
        (umulsidi3_sp64, const_umulsidi3_sp64): New patterns.
        (const_umulsidi3_sp32): Renamed from const_umulsidi3.
        (umulsidi3): Reflect this in the expand.
        (umulsi3_highpart): Only on TARGET_ARCH32.
        (divsi3_sp32): Renamed from divsi3, only on TARGET_ARCH32,
        don't require g0 to be zero.
        (udivsi3_sp32): Renamed from udivsi3, only on TARGET_ARCH32.
        ({,u}divsi3): New expands.
        ({,u}divsi3_sp64): New patterns.
        (after lshrdi3_v8plus): Four new patterns to help combiner
        optimizing nested mixed mode shifts.

        * config/sparc/sparc.c (sparc_override_options): Use deprecated
        v8 instructions if optimizing for UltraSPARC I, II, IIi, as it
        speed things up. Don't use them by default on plain v9 in 64bit
        mode, according to what SPAMv9 sais.

        * config/sparc/sparc.h: Fix comments, e.g. Linux already preserves
        top 32 bits of %[og][0-7] in signal handlers.
        Also, TARGET_HARD_MUL32 now is only true for TARGET_ARCH32.

From-SVN: r28346
parent cd531a2e
Showing with 55 additions and 13 deletions
gcc/ChangeLog
Fri Jul 30 14:53:56 1999 Jakub Jelinek <jj@ultra.linux.cz>
* config/sparc/linux64.h (CC1_SPEC): Preserve CPU specified by
the user if using the non-default arch size in BI_ARCH configuration.
* config/sparc/sol2-sld-64.h (CC1_SPEC): Ditto.
* config/sparc/sparc.md (cmp_mul_set, cmp_udiv_cc_set):
Fix patterns so that they actually match.
(cmp_sdiv_cc_set): Ditto, also don't require g0 to be zero.
(mulsidi3_sp64, const_mulsidi3_sp64): New patterns.
(const_mulsidi3_sp32): Renamed from const_mulsidi3, only on
TARGET_HARD_MUL32.
(mulsidi3): Reflect this in the expand.
(smulsi3_highpart): Only on TARGET_ARCH32.
(umulsidi3_sp64, const_umulsidi3_sp64): New patterns.
(const_umulsidi3_sp32): Renamed from const_umulsidi3.
(umulsidi3): Reflect this in the expand.
(umulsi3_highpart): Only on TARGET_ARCH32.
(divsi3_sp32): Renamed from divsi3, only on TARGET_ARCH32,
don't require g0 to be zero.
(udivsi3_sp32): Renamed from udivsi3, only on TARGET_ARCH32.
({,u}divsi3): New expands.
({,u}divsi3_sp64): New patterns.
(after lshrdi3_v8plus): Four new patterns to help combiner
optimizing nested mixed mode shifts.
* config/sparc/sparc.c (sparc_override_options): Use deprecated
v8 instructions if optimizing for UltraSPARC I, II, IIi, as it
speed things up. Don't use them by default on plain v9 in 64bit
mode, according to what SPAMv9 sais.
* config/sparc/sparc.h: Fix comments, e.g. Linux already preserves
top 32 bits of %[og][0-7] in signal handlers.
Also, TARGET_HARD_MUL32 now is only true for TARGET_ARCH32.
Fri Jul 30 03:00:41 1999 Jeffrey A Law (law@cygnus.com)
* pa.md (zvdep_imm32): Renamed from zvdep_imm.
......
gcc/config/sparc/linux64.h
......@@ -225,7 +225,8 @@ Boston, MA 02111-1307, USA. */
%{mcypress:-mcpu=cypress} \
%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
%{m64:-mptr64 -mcpu=ultrasparc -mstack-bias} \
%{m64:-mptr64 -mstack-bias \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:-mcpu=ultrasparc}}}}}}}} \
"
#else
#define CC1_SPEC "\
......@@ -233,7 +234,8 @@ Boston, MA 02111-1307, USA. */
%{mcypress:-mcpu=cypress} \
%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
%{m32:-mptr32 -mcpu=cypress -mno-stack-bias} \
%{m32:-mptr32 -mno-stack-bias \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:-mcpu=cypress}}}}}}}} \
"
#endif
......
gcc/config/sparc/sol2-sld-64.h
......@@ -244,7 +244,8 @@
%{mcypress:-mcpu=cypress} \
%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
%{m64:-mptr64 -mcpu=v9 -mstack-bias -mno-v8plus} \
%{m64:-mptr64 -mstack-bias -mno-v8plus \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8*:%{!msupersparc:-mcpu=v9}}}}}}}} \
"
#else
#define CC1_SPEC "\
......@@ -252,8 +253,10 @@
%{mcypress:-mcpu=cypress} \
%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
%{m32:-mptr32 -mcpu=cypress -mno-stack-bias} \
%{mv8plus:-m32 -mptr32 -mcpu=cypress -mno-stack-bias} \
%{m32:-mptr32 -mno-stack-bias \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8*:%{!msupersparc:-mcpu=cypress}}}}}}}} \
%{mv8plus:-m32 -mptr32 -mno-stack-bias \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:-mcpu=v9}}}}}}}} \
"
#endif
......
gcc/config/sparc/sparc.c
......@@ -213,8 +213,11 @@ sparc_override_options ()
/* TEMIC sparclet */
{ "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
{ "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
/* TI ultrasparc */
{ "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
/* TI ultrasparc I, II, IIi */
{ "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
/* Although insns using %y are deprecated, it is a clear win on current
ultrasparcs. */
|MASK_DEPRECATED_V8_INSNS },
{ 0, 0, 0, 0 }
};
struct cpu_table *cpu;
......
gcc/config/sparc/sparc.h
......@@ -50,11 +50,11 @@ Boston, MA 02111-1307, USA. */
/* Code model selection.
-mcmodel is used to select the v9 code model.
Different code models aren't supported for v8 code.
Different code models aren't supported for v7/8 code.
TARGET_CM_32: 32 bit address space, top 32 bits = 0,
pointers are 32 bits. Note that this isn't intended
to imply a v8 abi.
to imply a v7/8 abi.
TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
avoid generating %uhi and %ulo terms,
......@@ -542,9 +542,8 @@ extern int target_flags;
#define TARGET_VIS (target_flags & MASK_VIS)
/* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
the current out and global registers. Linux saves the high bits on
context switches but not signals. */
#define MASK_V8PLUS 0x2000000
the current out and global registers and Linux 2.2+ as well. */
#define MASK_V8PLUS 0x2000000
#define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
/* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
......@@ -555,7 +554,7 @@ extern int target_flags;
#define TARGET_HARD_MUL32 \
((TARGET_V8 || TARGET_SPARCLITE \
|| TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
&& ! TARGET_V8PLUS)
&& ! TARGET_V8PLUS && TARGET_ARCH32)
#define TARGET_HARD_MUL \
(TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
......
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