mips.h (ISA_HAS_BRANCHLIKELY): Remove TARGET_MIPS5500.

	* config/mips/mips.h (ISA_HAS_BRANCHLIKELY): Remove TARGET_MIPS5500.
	* config/mips/mips.c (override_options): Disable branch likely
	instructions if TUNE_MIPS5500.

From-SVN: r81624

gcc/ChangeLog

 2004-05-07  Richard Sandiford  <rsandifo@redhat.com>
 
+	* config/mips/mips.h (ISA_HAS_BRANCHLIKELY): Remove TARGET_MIPS5500.
+	* config/mips/mips.c (override_options): Disable branch likely
+	instructions if TUNE_MIPS5500.
+
+2004-05-07  Richard Sandiford  <rsandifo@redhat.com>
+
 	* config/mips/mips.c (override_options): Allow the hi and lo registers
 	to store any integral mode, not just MODE_INTs.
 

gcc/config/mips/mips.c

@@ -4744,7 +4744,7 @@ override_options (void)
 	 -mbranch-likely.  */
       if (ISA_HAS_BRANCHLIKELY
 	  && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
-	  && !(TUNE_SB1))
+	  && !(TUNE_MIPS5500 || TUNE_SB1))
 	target_flags |= MASK_BRANCHLIKELY;
       else
 	target_flags &= ~MASK_BRANCHLIKELY;

gcc/config/mips/mips.h

@@ -858,8 +858,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 /* ISA has branch likely instructions (eg. mips2).  */
 /* Disable branchlikely for tx39 until compare rewrite.  They haven't
    been generated up to this point.  */
-#define ISA_HAS_BRANCHLIKELY	(!ISA_MIPS1                             \
-				 && !TARGET_MIPS5500)
+#define ISA_HAS_BRANCHLIKELY	(!ISA_MIPS1)
 
 /* ISA has the conditional move instructions introduced in mips4.  */
 #define ISA_HAS_CONDMOVE        ((ISA_MIPS4				\