Commit 5c36be57 by Chung-Ju Wu Committed by Chung-Ju Wu

[NDS32] The add and sub pattens should only accept si mode.

gcc/
	* config/nds32/nds32.md (add<mode>3, sub<mode>3): Rename to ...
	(addsi3, subsi3): ... this.

From-SVN: r259116
parent 77827557
2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> 2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/nds32.md (add<mode>3, sub<mode>3): Rename to ...
(addsi3, subsi3): ... this.
2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/nds32.md (*sub_srli, *and_slli): Fine-tune predicator. * config/nds32/nds32.md (*sub_srli, *and_slli): Fine-tune predicator.
2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> 2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com>
......
...@@ -320,10 +320,10 @@ ...@@ -320,10 +320,10 @@
;; Arithmetic instructions. ;; Arithmetic instructions.
(define_insn "add<mode>3" (define_insn "addsi3"
[(set (match_operand:QIHISI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r") [(set (match_operand:SI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r")
(plus:QIHISI (match_operand:QIHISI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r") (plus:SI (match_operand:SI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r")
(match_operand:QIHISI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03, r, l, Is10, Iu06, Is15, r")))] (match_operand:SI 2 "nds32_rimm15s_operand" " In05,In03,Iu05,Iu03, r, l,Is10,IU06, Is15, r")))]
"" ""
{ {
switch (which_alternative) switch (which_alternative)
...@@ -363,10 +363,10 @@ ...@@ -363,10 +363,10 @@
(set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4") (set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4")
(set_attr "feature" " v1, v1, v1, v1, v1, v1, v2, v1, v1, v1")]) (set_attr "feature" " v1, v1, v1, v1, v1, v1, v2, v1, v1, v1")])
(define_insn "sub<mode>3" (define_insn "subsi3"
[(set (match_operand:QIHISI 0 "register_operand" "=d, l, r, r") [(set (match_operand:SI 0 "register_operand" "=d, l, r, r")
(minus:QIHISI (match_operand:QIHISI 1 "nds32_rimm15s_operand" " 0, l, Is15, r") (minus:SI (match_operand:SI 1 "nds32_rimm15s_operand" " 0, l, Is15, r")
(match_operand:QIHISI 2 "register_operand" " r, l, r, r")))] (match_operand:SI 2 "register_operand" " r, l, r, r")))]
"" ""
"@ "@
sub45\t%0, %2 sub45\t%0, %2
......
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