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Commit 5c0a2e3a by Richard Sandiford Committed by Richard Sandiford
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mips.h (reg_class): Remove HI_AND_GR_REGS... 

gcc/
	* config/mips/mips.h (reg_class): Remove HI_AND_GR_REGS,
	LO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS,
	COP3_AND_GR_REGS, ALL_COP_REGS and ALL_COP_AND_GR_REGS.
	Add GR_AND_MD0_REGS, GR_AND_MD1_REGS, GR_AND_MD_REGS and
	GR_AND_ACC_REGS.
	(REG_CLASS_NAMES): Update accordingly.
	(REG_CLASS_CONTENTS): Likewise.  Use the class name in the comments,
	rather than an unpredictable descriptive string.
	* config/mips/mips.c (mips_register_move_cost): Remove comment.
	(mips_register_move_cost): Check for specific COP*_REGS classes,
	instead of ALL_COP_AND_GR_REGS.
	(mips_ira_cover_classes): New function.
	(mips_secondary_reload_class): Remove MTLO and MTHI workarounds.
	(TARGET_IRA_COVER_CLASSES): Define.

From-SVN: r141117
parent b17c40be
Showing with 77 additions and 54 deletions
gcc/ChangeLog
2008-10-14 Richard Sandiford <rdsandiford@googlemail.com>
* config/mips/mips.h (reg_class): Remove HI_AND_GR_REGS,
LO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS,
COP3_AND_GR_REGS, ALL_COP_REGS and ALL_COP_AND_GR_REGS.
Add GR_AND_MD0_REGS, GR_AND_MD1_REGS, GR_AND_MD_REGS and
GR_AND_ACC_REGS.
(REG_CLASS_NAMES): Update accordingly.
(REG_CLASS_CONTENTS): Likewise. Use the class name in the comments,
rather than an unpredictable descriptive string.
* config/mips/mips.c (mips_register_move_cost): Remove comment.
(mips_register_move_cost): Check for specific COP*_REGS classes,
instead of ALL_COP_AND_GR_REGS.
(mips_ira_cover_classes): New function.
(mips_secondary_reload_class): Remove MTLO and MTHI workarounds.
(TARGET_IRA_COVER_CLASSES): Define.
2008-10-14 Douglas Gregor <doug.gregor@gmail.com> 2008-10-14 Douglas Gregor <doug.gregor@gmail.com>
PR c++/37553 PR c++/37553
......
gcc/config/mips/mips.c
...@@ -9697,10 +9697,6 @@ mips_register_move_cost (enum machine_mode mode, ...@@ -9697,10 +9697,6 @@ mips_register_move_cost (enum machine_mode mode,
{ {
if (TARGET_MIPS16) if (TARGET_MIPS16)
{ {
/* ??? We cannot move general registers into HI and LO because
MIPS16 has no MTHI and MTLO instructions. Make the cost of
moves in the opposite direction just as high, which stops the
register allocators from using HI and LO for pseudos. */
if (reg_class_subset_p (from, GENERAL_REGS) if (reg_class_subset_p (from, GENERAL_REGS)
&& reg_class_subset_p (to, GENERAL_REGS)) && reg_class_subset_p (to, GENERAL_REGS))
{ {
...@@ -9717,7 +9713,9 @@ mips_register_move_cost (enum machine_mode mode, ...@@ -9717,7 +9713,9 @@ mips_register_move_cost (enum machine_mode mode,
return 2; return 2;
if (reg_class_subset_p (to, FP_REGS)) if (reg_class_subset_p (to, FP_REGS))
return 4; return 4;
if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS)) if (reg_class_subset_p (to, COP0_REGS)
|| reg_class_subset_p (to, COP2_REGS)
|| reg_class_subset_p (to, COP3_REGS))
return 5; return 5;
if (reg_class_subset_p (to, ACC_REGS)) if (reg_class_subset_p (to, ACC_REGS))
return 6; return 6;
...@@ -9729,7 +9727,9 @@ mips_register_move_cost (enum machine_mode mode, ...@@ -9729,7 +9727,9 @@ mips_register_move_cost (enum machine_mode mode,
if (reg_class_subset_p (from, ST_REGS)) if (reg_class_subset_p (from, ST_REGS))
/* LUI followed by MOVF. */ /* LUI followed by MOVF. */
return 4; return 4;
if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS)) if (reg_class_subset_p (from, COP0_REGS)
|| reg_class_subset_p (from, COP2_REGS)
|| reg_class_subset_p (from, COP3_REGS))
return 5; return 5;
if (reg_class_subset_p (from, ACC_REGS)) if (reg_class_subset_p (from, ACC_REGS))
return 6; return 6;
...@@ -9747,6 +9747,25 @@ mips_register_move_cost (enum machine_mode mode, ...@@ -9747,6 +9747,25 @@ mips_register_move_cost (enum machine_mode mode,
return 12; return 12;
} }
/* Implement TARGET_IRA_COVER_CLASSES. */
static const enum reg_class *
mips_ira_cover_classes (void)
{
static const enum reg_class acc_classes[] = {
GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
ST_REGS, LIM_REG_CLASSES
};
static const enum reg_class no_acc_classes[] = {
GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
ST_REGS, LIM_REG_CLASSES
};
/* Don't allow the register allocators to use LO and HI in MIPS16 mode,
which has no MTLO or MTHI instructions. */
return TARGET_MIPS16 ? no_acc_classes : acc_classes;
}
/* Return the register class required for a secondary register when /* Return the register class required for a secondary register when
copying between one of the registers in RCLASS and value X, which copying between one of the registers in RCLASS and value X, which
has mode MODE. X is the source of the move if IN_P, otherwise it has mode MODE. X is the source of the move if IN_P, otherwise it
...@@ -9771,10 +9790,6 @@ mips_secondary_reload_class (enum reg_class rclass, ...@@ -9771,10 +9790,6 @@ mips_secondary_reload_class (enum reg_class rclass,
if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno)) if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
return M16_REGS; return M16_REGS;
/* We can't really copy to HI or LO at all in MIPS16 mode. */
if (in_p ? reg_classes_intersect_p (rclass, ACC_REGS) : ACC_REG_P (regno))
return M16_REGS;
return NO_REGS; return NO_REGS;
} }
...@@ -14203,6 +14218,9 @@ mips_order_regs_for_local_alloc (void) ...@@ -14203,6 +14218,9 @@ mips_order_regs_for_local_alloc (void)
#undef TARGET_DWARF_REGISTER_SPAN #undef TARGET_DWARF_REGISTER_SPAN
#define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
#undef TARGET_IRA_COVER_CLASSES
#define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
struct gcc_target targetm = TARGET_INITIALIZER; struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-mips.h" #include "gt-mips.h"
gcc/config/mips/mips.h
...@@ -1796,18 +1796,14 @@ enum reg_class ...@@ -1796,18 +1796,14 @@ enum reg_class
COP0_REGS, /* generic coprocessor classes */ COP0_REGS, /* generic coprocessor classes */
COP2_REGS, COP2_REGS,
COP3_REGS, COP3_REGS,
HI_AND_GR_REGS, /* union classes */
LO_AND_GR_REGS,
HI_AND_FP_REGS,
COP0_AND_GR_REGS,
COP2_AND_GR_REGS,
COP3_AND_GR_REGS,
ALL_COP_REGS,
ALL_COP_AND_GR_REGS,
ST_REGS, /* status registers (fp status) */ ST_REGS, /* status registers (fp status) */
DSP_ACC_REGS, /* DSP accumulator registers */ DSP_ACC_REGS, /* DSP accumulator registers */
ACC_REGS, /* Hi/Lo and DSP accumulator registers */ ACC_REGS, /* Hi/Lo and DSP accumulator registers */
FRAME_REGS, /* $arg and $frame */ FRAME_REGS, /* $arg and $frame */
GR_AND_MD0_REGS, /* union classes */
GR_AND_MD1_REGS,
GR_AND_MD_REGS,
GR_AND_ACC_REGS,
ALL_REGS, /* all registers */ ALL_REGS, /* all registers */
LIM_REG_CLASSES /* max value + 1 */ LIM_REG_CLASSES /* max value + 1 */
}; };
...@@ -1838,18 +1834,14 @@ enum reg_class ...@@ -1838,18 +1834,14 @@ enum reg_class
"COP0_REGS", \ "COP0_REGS", \
"COP2_REGS", \ "COP2_REGS", \
"COP3_REGS", \ "COP3_REGS", \
"HI_AND_GR_REGS", \
"LO_AND_GR_REGS", \
"HI_AND_FP_REGS", \
"COP0_AND_GR_REGS", \
"COP2_AND_GR_REGS", \
"COP3_AND_GR_REGS", \
"ALL_COP_REGS", \
"ALL_COP_AND_GR_REGS", \
"ST_REGS", \ "ST_REGS", \
"DSP_ACC_REGS", \ "DSP_ACC_REGS", \
"ACC_REGS", \ "ACC_REGS", \
"FRAME_REGS", \ "FRAME_REGS", \
"GR_AND_MD0_REGS", \
"GR_AND_MD1_REGS", \
"GR_AND_MD_REGS", \
"GR_AND_ACC_REGS", \
"ALL_REGS" \ "ALL_REGS" \
} }
...@@ -1866,34 +1858,30 @@ enum reg_class ...@@ -1866,34 +1858,30 @@ enum reg_class
#define REG_CLASS_CONTENTS \ #define REG_CLASS_CONTENTS \
{ \ { \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \ { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \ { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \ { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
{ 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \ { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
{ 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \ { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
{ 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \ { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \ { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \ { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \ { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \ { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
{ 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \ { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
{ 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \ { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
{ 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \ { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
{ 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
{ 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \ { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
{ 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \ { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
{ 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \ { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \ { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
{ 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
{ 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
{ 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \ { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
{ 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* frame registers */ \
{ 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
} }
......
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