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riscv-gcc-1
Commit 5bb77598 by H.J. Lu Committed by H.J. Lu
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i386.c (contains_aligned_value_p): Return true for __float128. 

2008-06-30  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c (contains_aligned_value_p): Return true
	for __float128.
	(ix86_function_arg_boundary): Return its natural boundary for
	for __float128.
	(return_in_memory_32): Don't check TDmode.
	(ix86_split_to_parts): Support splitting into 4 parts and
	support TFmode for 32bit target.
	(ix86_split_long_move): Support splitting into 4 parts.
	(bdesc_args): Enable IX86_BUILTIN_FABSQ and IX86_BUILTIN_COPYSIGNQ
	for SSE2.
	(ix86_init_mmx_sse_builtins): Move __float80 and __float128
	to ...
	(ix86_init_builtins): Here.
	(ix86_scalar_mode_supported_p): Always return true for TFmode.
	(ix86_c_mode_for_suffix): Always return TFmode and XFmode for
	'q' and 'w', respectively. 

	* config/i386/i386.md (movtf): Check TARGET_SSE2 instead of
	TARGET_64BIT.
	(movtf_internal): Likewise.
	(<code>tf2): Likewise.
	(*absnegtf2_sse): Likewise.
	(copysign<mode>3): Likewise.
	(copysign<mode>3_const): Likewise.
	(copysign<mode>3_var): Likewise.
	(define_split UNSPEC_COPYSIGN): Likewise.
	* config/i386/sse.md (*nandtf3): Likewise.
	(<code>tf3): Likewise.
	(*<code>tf3): Likewise.

From-SVN: r137276
parent 38aa4d08
Showing with 43 additions and 11 deletions
gcc/ChangeLog
2008-06-30 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.c (contains_aligned_value_p): Return true
for __float128.
(ix86_function_arg_boundary): Return its natural boundary for
for __float128.
(return_in_memory_32): Don't check TDmode.
(ix86_split_to_parts): Support splitting into 4 parts and
support TFmode for 32bit target.
(ix86_split_long_move): Support splitting into 4 parts.
(bdesc_args): Enable IX86_BUILTIN_FABSQ and IX86_BUILTIN_COPYSIGNQ
for SSE2.
(ix86_init_mmx_sse_builtins): Move __float80 and __float128
to ...
(ix86_init_builtins): Here.
(ix86_scalar_mode_supported_p): Always return true for TFmode.
(ix86_c_mode_for_suffix): Always return TFmode and XFmode for
'q' and 'w', respectively.
* config/i386/i386.md (movtf): Check TARGET_SSE2 instead of
TARGET_64BIT.
(movtf_internal): Likewise.
(<code>tf2): Likewise.
(*absnegtf2_sse): Likewise.
(copysign<mode>3): Likewise.
(copysign<mode>3_const): Likewise.
(copysign<mode>3_var): Likewise.
(define_split UNSPEC_COPYSIGN): Likewise.
* config/i386/sse.md (*nandtf3): Likewise.
(<code>tf3): Likewise.
(*<code>tf3): Likewise.
2008-06-30 Joey Ye <joey.ye@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
......
gcc/config/i386/i386.md
......@@ -3261,7 +3261,7 @@
(define_expand "movtf"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "nonimmediate_operand" ""))]
"TARGET_64BIT"
"TARGET_SSE2"
{
ix86_expand_move (TFmode, operands);
DONE;
......@@ -3270,7 +3270,7 @@
(define_insn "*movtf_internal"
[(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?r,?o")
(match_operand:TF 1 "general_operand" "xm,x,C,roF,Fr"))]
"TARGET_64BIT
"TARGET_SSE2
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (which_alternative)
......@@ -10348,7 +10348,7 @@
(define_expand "<code>tf2"
[(set (match_operand:TF 0 "register_operand" "")
(absneg:TF (match_operand:TF 1 "register_operand" "")))]
"TARGET_64BIT"
"TARGET_SSE2"
"ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
(define_insn "*absnegtf2_sse"
......@@ -10357,7 +10357,7 @@
[(match_operand:TF 1 "register_operand" "0,x")]))
(use (match_operand:TF 2 "nonimmediate_operand" "xm,0"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"TARGET_SSE2"
"#")
;; Splitters for fp abs and neg.
......@@ -10536,7 +10536,7 @@
(match_operand:CSGNMODE 1 "nonmemory_operand" "")
(match_operand:CSGNMODE 2 "register_operand" "")]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| (TARGET_64BIT && (<MODE>mode == TFmode))"
|| (TARGET_SSE2 && (<MODE>mode == TFmode))"
{
ix86_expand_copysign (operands);
DONE;
......@@ -10550,7 +10550,7 @@
(match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "xm")]
UNSPEC_COPYSIGN))]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| (TARGET_64BIT && (<MODE>mode == TFmode))"
|| (TARGET_SSE2 && (<MODE>mode == TFmode))"
"#"
"&& reload_completed"
[(const_int 0)]
......@@ -10569,7 +10569,7 @@
UNSPEC_COPYSIGN))
(clobber (match_scratch:<CSGNVMODE> 1 "=x,x,x,x,x"))]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| (TARGET_64BIT && (<MODE>mode == TFmode))"
|| (TARGET_SSE2 && (<MODE>mode == TFmode))"
"#")
(define_split
......@@ -10582,7 +10582,7 @@
UNSPEC_COPYSIGN))
(clobber (match_scratch:<CSGNVMODE> 1 ""))]
"((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| (TARGET_64BIT && (<MODE>mode == TFmode)))
|| (TARGET_SSE2 && (<MODE>mode == TFmode)))
&& reload_completed"
[(const_int 0)]
{
......
gcc/config/i386/sse.md
......@@ -3895,7 +3895,7 @@
(and:TF
(not:TF (match_operand:TF 1 "register_operand" "0"))
(match_operand:TF 2 "nonimmediate_operand" "xm")))]
"TARGET_64BIT"
"TARGET_SSE2"
"pandn\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
......@@ -3936,7 +3936,7 @@
(plogic:TF
(match_operand:TF 1 "nonimmediate_operand" "")
(match_operand:TF 2 "nonimmediate_operand" "")))]
"TARGET_64BIT"
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
(define_insn "*<code>tf3"
......@@ -3944,7 +3944,7 @@
(plogic:TF
(match_operand:TF 1 "nonimmediate_operand" "%0")
(match_operand:TF 2 "nonimmediate_operand" "xm")))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
"p<plogicprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
......
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