sparc.h (AS_NIAGARA3_FLAG): Tweak.

	* config/sparc/sparc.h (AS_NIAGARA3_FLAG): Tweak.
	* config/sparc/sol2.h (TARGET_CPU_niagara4 support): Fix pasto.

From-SVN: r193416

gcc/ChangeLog

 2012-11-11  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc.h (AS_NIAGARA3_FLAG): Tweak.
+	* config/sparc/sol2.h (TARGET_CPU_niagara4 support): Fix pasto.
+
+2012-11-11  Eric Botcazou  <ebotcazou@adacore.com>
 	    H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR rtl-optimization/55247

gcc/config/sparc/sol2.h

@@ -136,9 +136,9 @@ along with GCC; see the file COPYING3.  If not see
 #undef CPP_CPU64_DEFAULT_SPEC
 #define CPP_CPU64_DEFAULT_SPEC ""
 #undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus" AS_NIAGARA3_FLAG
 #undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA3_FLAG
 #undef ASM_CPU_DEFAULT_SPEC
 #define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC
 #endif

gcc/config/sparc/sparc.h

@@ -1740,10 +1740,10 @@ extern int sparc_indent_opcode;
 #define TARGET_SUN_TLS TARGET_TLS
 #define TARGET_GNU_TLS 0
 
-#ifndef HAVE_AS_FMAF_HPC_VIS3
-#define AS_NIAGARA3_FLAG "b"
-#else
+#ifdef HAVE_AS_FMAF_HPC_VIS3
 #define AS_NIAGARA3_FLAG "d"
+#else
+#define AS_NIAGARA3_FLAG "b"
 #endif
 
 /* We use gcc _mcount for profiling.  */