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riscv-gcc-1
Commit 5ad82096 by Kyrylo Tkachov Committed by Kyrylo Tkachov
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[ARM] Add source mode to coprocessor pattern SETs 

	* config/arm/arm.md (<mrc>): Add mode to SET source.
	(<mrrc>): Likewise.

From-SVN: r246801
parent cd7fac96
Showing with 7 additions and 2 deletions
gcc/ChangeLog
2016-04-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (<mrc>): Add mode to SET source.
(<mrrc>): Likewise.
2017-04-10 Richard Biener <rguenther@suse.de>
PR middle-end/80344
......
gcc/config/arm/arm.md
......@@ -12009,7 +12009,7 @@
(define_insn "<mrc>"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(unspec_volatile [(match_operand:SI 1 "immediate_operand" "n")
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "n")
(match_operand:SI 2 "immediate_operand" "n")
(match_operand:SI 3 "immediate_operand" "n")
(match_operand:SI 4 "immediate_operand" "n")
......@@ -12044,7 +12044,7 @@
(define_insn "<mrrc>"
[(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec_volatile [(match_operand:SI 1 "immediate_operand" "n")
(unspec_volatile:DI [(match_operand:SI 1 "immediate_operand" "n")
(match_operand:SI 2 "immediate_operand" "n")
(match_operand:SI 3 "immediate_operand" "n")] MRRCI))]
"arm_coproc_builtin_available (VUNSPEC_<MRRC>)"
......
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