genrecog.c: Include regs.h in generated file.

2007-05-30  Eric Christopher  <echristo@gmail.com>

	* genrecog.c: Include regs.h in generated file.
	* genemit.c: Ditto. Fix up formatting.
	* config/mn10300/constraints.md: New.
	* config/mn10300/mn10300.md: Include.
	* config/mn10300/mn10300.c(mn10300_secondary_reload_class):
	Fix up for removed macro.
	* config/mn10300/predicates.md (call_address_operand):  Ditto.
	* config/mn10300/mn10300.h (REG_CLASS_FROM_LETTER): Delete.
	(CONST_OK_FOR_I): Ditto.
	(CONST_OK_FOR_J): Ditto.
	(CONST_OK_FOR_K): Ditto.
	(CONST_OK_FOR_L): Ditto.
	(CONST_OK_FOR_M): Ditto.
	(CONST_OK_FOR_N): Ditto.
	(CONST_DOUBLE_OK_FOR_LETTER_P): Ditto.
	(OK_FOR_Q): Ditto.
	(OK_FOR_R): Ditto.
	(OK_FOR_T): Ditto.
	(EXTRA_CONSTRAINT): Ditto.

From-SVN: r125192

gcc/ChangeLog

+2007-05-30  Eric Christopher  <echristo@gmail.com>
+
+	* genrecog.c: Include regs.h in generated file.
+	* genemit.c: Ditto. Fix up formatting.
+	* config/mn10300/constraints.md: New.
+	* config/mn10300/mn10300.md: Include.
+	* config/mn10300/mn10300.c(mn10300_secondary_reload_class):
+	Fix up for removed macro.
+	* config/mn10300/predicates.md (call_address_operand):  Ditto.
+	* config/mn10300/mn10300.h (REG_CLASS_FROM_LETTER): Delete.
+	(CONST_OK_FOR_I): Ditto.
+	(CONST_OK_FOR_J): Ditto.
+	(CONST_OK_FOR_K): Ditto.
+	(CONST_OK_FOR_L): Ditto.
+	(CONST_OK_FOR_M): Ditto.
+	(CONST_OK_FOR_N): Ditto.
+	(CONST_DOUBLE_OK_FOR_LETTER_P): Ditto.
+	(OK_FOR_Q): Ditto.
+	(OK_FOR_R): Ditto.
+	(OK_FOR_T): Ditto.
+	(EXTRA_CONSTRAINT): Ditto.
+
 2007-05-30 Uros Bizjak <ubizjak@gmail.com>
 
 	* config/i386/i386.h (MASK_64BIT, MASK_MMX, MASK_3DNOW*, MASK_SSE*):
@@ -97,7 +119,7 @@
 	NOTE_INSN_PROLOGUE_END at beginning of the thunk.
 
 2007-05-29  Hui-May Chang  <hm.chang@apple.com>
-	* config/i386/i386.c (ix86_function_regparm): Added checking of 
+	* config/i386/i386.c (ix86_function_regparm): Added checking of
 	ix86_force_align_arg_pointer to determine the number of
 	register parameters.
 
@@ -199,9 +221,9 @@
 	* target/i386/i386.c (ix86_expand_vector_move): Expand unaligned
 	memory access via x86_expand_vector_move_misalign() only for
 	TImode values on 32-bit targets.
-	
-2007-05-28  Razya Ladelsky  <razya@il.ibm.com>  
-        
+
+2007-05-28  Razya Ladelsky  <razya@il.ibm.com>
+
 	* matrix-reorg.c: New file. Implement matrix flattening and
 	transposing optimization.
 	* tree-pass.h: Add matrix reorg pass.

gcc/config/mn10300/constraints.md

+;; Constraint definitions for the MN10300.
+;; Copyright (C) 2007 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
+
+(define_register_constraint "d" "DATA_REGS"
+  "A data register.")
+
+(define_register_constraint "a" "ADDRESS_REGS"
+  "An address register.")
+
+(define_register_constraint "y" "SP_REGS"
+  "An SP register (if available).")
+
+(define_register_constraint "x" "TARGET_AM33 ? EXTENDED_REGS : NO_REGS"
+  "An extended register.")
+
+(define_register_constraint "f" "TARGET_AM33_2 ? FP_REGS : NO_REGS"
+  "A floating point register.")
+
+(define_register_constraint "A" "TARGET_AM33_2 ? FP_ACC_REGS : NO_REGS"
+  "A floating point accumulator register.")
+
+(define_memory_constraint "Q"
+  "@internal"
+  (and (match_code "mem")
+       (match_test "!CONSTANT_ADDRESS_P (XEXP (op, 0))")))
+
+(define_memory_constraint "R"
+  "@internal"
+  (and (match_code "mem")
+       (match_test "mode == QImode")
+       (ior (match_test "CONSTANT_ADDRESS_P (XEXP (op, 0))")
+	    (and (match_test "GET_CODE (XEXP (op, 0)) == REG")
+		 (match_test "REG_OK_FOR_BIT_BASE_P (XEXP (op, 0))")
+		 (match_test "XEXP (op, 0) != stack_pointer_rtx"))
+	    (and (match_test "GET_CODE (XEXP (op, 0)) == PLUS")
+		 (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == REG")
+		 (match_test "REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (op, 0), 0))")
+		 (match_test "XEXP (XEXP (op, 0), 0) != stack_pointer_rtx")
+		 (match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT")
+		 (match_test "INT_8_BITS (INTVAL (XEXP (XEXP (op, 0), 1)))")))))
+
+(define_memory_constraint "T"
+  "@internal"
+  (and (match_code "mem")
+       (match_test "mode == QImode")
+       (and (match_test "GET_CODE (XEXP (op, 0)) == REG")
+	    (match_test "REG_OK_FOR_BIT_BASE_P (XEXP (op, 0))")
+	    (match_test "XEXP (op, 0) != stack_pointer_rtx"))))
+
+(define_constraint "S"
+  "@internal"
+  (if_then_else (match_test "flag_pic")
+	(and (match_test "GET_CODE (op) == UNSPEC")
+	     (ior (match_test "XINT (op, 1) == UNSPEC_PLT")
+		  (match_test "XINT (op, 1) == UNSPEC_PIC")))
+	(match_test "GET_CODE (op) == SYMBOL_REF")))
+
+;; Integer constraints
+
+(define_constraint "I"
+  "An integer zero."
+  (and (match_code "const_int")
+       (match_test "ival == 0")))
+
+(define_constraint "J"
+  "An integer one."
+  (and (match_code "const_int")
+       (match_test "ival == 1")))
+
+(define_constraint "K"
+  "An integer two."
+  (and (match_code "const_int")
+       (match_test "ival == 2")))
+
+(define_constraint "L"
+  "An integer four."
+  (and (match_code "const_int")
+       (match_test "ival == 4")))
+
+(define_constraint "M"
+  "An integer three."
+  (and (match_code "const_int")
+       (match_test "ival == 3")))
+
+(define_constraint "N"
+  "An integer of either 255 or 65535."
+  (and (match_code "const_int")
+       (ior (match_test "ival == 255")
+	    (match_test "ival == 65535"))))
+
+;; Floating-point constraints
+(define_constraint "G"
+  "Floating-point zero."
+  (and (match_code "const_double")
+       (match_test "op == CONST0_RTX (mode)")))

gcc/config/mn10300/mn10300.c

@@ -274,7 +274,7 @@ print_operand (FILE *file, rtx x, int code)
 	else
 	  print_operand (file, x, 0);
 	break;
-     
+
       case 'D':
 	switch (GET_CODE (x))
 	  {
@@ -387,7 +387,7 @@ print_operand (FILE *file, rtx x, int code)
 		      gcc_unreachable ();
 		    case VOIDmode:
 		    case DImode:
-		      print_operand_address (file, 
+		      print_operand_address (file,
 					     GEN_INT (CONST_DOUBLE_HIGH (x)));
 		      break;
 		    default:
@@ -882,7 +882,7 @@ expand_prologue (void)
 	default:
 	  gcc_unreachable ();
 	}
-	  
+
       /* Now prepare register a0, if we have decided to use it.  */
       switch (strategy)
 	{
@@ -900,11 +900,11 @@ expand_prologue (void)
 	    emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
 	  reg = gen_rtx_POST_INC (SImode, reg);
 	  break;
-	  
+
 	default:
 	  gcc_unreachable ();
 	}
-      
+
       /* Now actually save the FP registers.  */
       for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
 	if (regs_ever_live[i] && ! call_used_regs[i])
@@ -924,7 +924,7 @@ expand_prologue (void)
 		  }
 		else
 		  addr = stack_pointer_rtx;
-		
+
 		xsize += 4;
 	      }
 
@@ -1109,7 +1109,7 @@ expand_epilogue (void)
 					      + REG_SAVE_BYTES - 252)));
 	      size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
 	      break;
-	      
+
 	    case restore_a1:
 	      reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
 	      emit_insn (gen_movsi (reg, stack_pointer_rtx));
@@ -1130,7 +1130,7 @@ expand_epilogue (void)
 	if (regs_ever_live[i] && ! call_used_regs[i])
 	  {
 	    rtx addr;
-	    
+
 	    if (reg)
 	      addr = reg;
 	    else if (size)
@@ -1167,7 +1167,7 @@ expand_epilogue (void)
 
      If the stack size + register save area is more than 255 bytes,
      then the stack must be cut back here since the size + register
-     save size is too big for a ret/retf instruction. 
+     save size is too big for a ret/retf instruction.
 
      Else leave it alone, it will be cut back as part of the
      ret/retf instruction, or there wasn't any stack to begin with.
@@ -1333,7 +1333,7 @@ store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 }
 
 /* What (if any) secondary registers are needed to move IN with mode
-   MODE into a register in register class CLASS. 
+   MODE into a register in register class CLASS.
 
    We might be able to simplify this.  */
 enum reg_class
@@ -1380,9 +1380,10 @@ mn10300_secondary_reload_class (enum reg_class class, enum machine_mode mode,
 	return DATA_OR_EXTENDED_REGS;
       return DATA_REGS;
     }
- 
+
   if (TARGET_AM33_2 && class == FP_REGS
-      && GET_CODE (in) == MEM && ! OK_FOR_Q (in))
+      && GET_CODE (in) == MEM
+      && ! (GET_CODE (in) == MEM && !CONSTANT_ADDRESS_P (XEXP (in, 0))))
     {
       if (TARGET_AM33)
 	return DATA_OR_EXTENDED_REGS;
@@ -1426,11 +1427,11 @@ initial_offset (int from, int to)
 	return (get_frame_size () + REG_SAVE_BYTES
 		+ 4 * fp_regs_to_save ()
 		+ (current_function_outgoing_args_size
-		   ? current_function_outgoing_args_size + 4 : 0)); 
+		   ? current_function_outgoing_args_size + 4 : 0));
       else
 	return (get_frame_size ()
 		+ (current_function_outgoing_args_size
-		   ? current_function_outgoing_args_size + 4 : 0)); 
+		   ? current_function_outgoing_args_size + 4 : 0));
     }
 
   /* The difference between the frame pointer and stack pointer is the sum
@@ -1439,7 +1440,7 @@ initial_offset (int from, int to)
   if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
     return (get_frame_size ()
 	    + (current_function_outgoing_args_size
-	       ? current_function_outgoing_args_size + 4 : 0)); 
+	       ? current_function_outgoing_args_size + 4 : 0));
 
   gcc_unreachable ();
 }
@@ -1624,7 +1625,7 @@ mn10300_function_value (tree valtype, tree func, int outgoing)
     = gen_rtx_EXPR_LIST (VOIDmode,
 			 gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
 			 GEN_INT (0));
-  
+
   XVECEXP (rv, 0, 1)
     = gen_rtx_EXPR_LIST (VOIDmode,
 			 gen_rtx_REG (mode, FIRST_DATA_REGNUM),
@@ -1672,7 +1673,7 @@ output_tst (rtx operand, rtx insn)
 	}
 
       /* Are we setting a data register to zero (this does not win for
-	 address registers)? 
+	 address registers)?
 
 	 If it's a call clobbered register, have we past a call?
 
@@ -1688,7 +1689,7 @@ output_tst (rtx operand, rtx insn)
 	      == REGNO_REG_CLASS (REGNO (operand)))
 	  && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
 	  && REGNO (SET_DEST (set)) != REGNO (operand)
-	  && (!past_call 
+	  && (!past_call
 	      || !call_used_regs[REGNO (SET_DEST (set))]))
 	{
 	  rtx xoperands[2];
@@ -1707,7 +1708,7 @@ output_tst (rtx operand, rtx insn)
 	      != REGNO_REG_CLASS (REGNO (operand)))
 	  && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
 	  && REGNO (SET_DEST (set)) != REGNO (operand)
-	  && (!past_call 
+	  && (!past_call
 	      || !call_used_regs[REGNO (SET_DEST (set))]))
 	{
 	  rtx xoperands[2];
@@ -2087,7 +2088,7 @@ mn10300_wide_const_load_uses_clr (rtx operands[2])
 	val[1] = INTVAL (high);
       }
       break;
-      
+
     case CONST_DOUBLE:
       if (GET_MODE (operands[1]) == DFmode)
 	{
@@ -2103,7 +2104,7 @@ mn10300_wide_const_load_uses_clr (rtx operands[2])
 	  val[1] = CONST_DOUBLE_HIGH (operands[1]);
 	}
       break;
-      
+
     default:
       return false;
     }

gcc/config/mn10300/mn10300.h

@@ -251,12 +251,12 @@ extern enum processor_type mn10300_processor;
 
    For any two classes, it is very desirable that there be another
    class that represents their union.  */
-   
+
 enum reg_class {
   NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
-  DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, 
+  DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
   EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS,
-  SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, 
+  SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS,
   FP_REGS, FP_ACC_REGS,
   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
 };
@@ -313,19 +313,6 @@ enum reg_class {
 #define INDEX_REG_CLASS DATA_OR_EXTENDED_REGS
 #define BASE_REG_CLASS  SP_OR_ADDRESS_REGS
 
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'd' ? DATA_REGS : \
-   (C) == 'a' ? ADDRESS_REGS : \
-   (C) == 'y' ? SP_REGS : \
-   ! TARGET_AM33 ? NO_REGS : \
-   (C) == 'x' ? EXTENDED_REGS : \
-   ! TARGET_AM33_2 ? NO_REGS : \
-   (C) == 'f' ? FP_REGS : \
-   (C) == 'A' ? FP_ACC_REGS : \
-   NO_REGS)
-
 /* Macros to check register numbers against specific register classes.  */
 
 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
@@ -440,40 +427,11 @@ enum reg_class {
    loaded the register.  */
 #define CLASS_CANNOT_CHANGE_SIZE FP_REGS
 
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
+/* Return 1 if VALUE is in the range specified.  */
 
 #define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
 #define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
 
-#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
-#define CONST_OK_FOR_J(VALUE) ((VALUE) == 1)
-#define CONST_OK_FOR_K(VALUE) ((VALUE) == 2)
-#define CONST_OK_FOR_L(VALUE) ((VALUE) == 4)
-#define CONST_OK_FOR_M(VALUE) ((VALUE) == 3)
-#define CONST_OK_FOR_N(VALUE) ((VALUE) == 255 || (VALUE) == 65535)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
-   (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
-   (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
-   (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
-   (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
-   (C) == 'N' ? CONST_OK_FOR_N (VALUE) : 0)
-
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself. 
-     
-  `G' is a floating-point zero.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT	\
-		 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) : 0)
-
 
 /* Stack layout; function entry, exit and calling.  */
 
@@ -585,7 +543,7 @@ struct cum_arg {int nbytes; };
    NAMED is nonzero if this argument is a named parameter
     (otherwise it is an extra parameter matching an ellipsis).  */
 
-/* On the MN10300 all args are pushed.  */   
+/* On the MN10300 all args are pushed.  */
 
 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
   function_arg (&CUM, MODE, TYPE, NAMED)
@@ -676,42 +634,6 @@ struct cum_arg {int nbytes; };
 
 #define CONSTANT_ADDRESS_P(X)   CONSTANT_P (X)
 
-/* Extra constraints.  */
- 
-#define OK_FOR_Q(OP) \
-   (GET_CODE (OP) == MEM && ! CONSTANT_ADDRESS_P (XEXP (OP, 0)))
-
-#define OK_FOR_R(OP) \
-   (GET_CODE (OP) == MEM					\
-    && GET_MODE (OP) == QImode					\
-    && (CONSTANT_ADDRESS_P (XEXP (OP, 0))			\
-	|| (GET_CODE (XEXP (OP, 0)) == REG			\
-	    && REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0))		\
-	    && XEXP (OP, 0) != stack_pointer_rtx)		\
-	|| (GET_CODE (XEXP (OP, 0)) == PLUS			\
-	    && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG		\
-	    && REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (OP, 0), 0))	\
-	    && XEXP (XEXP (OP, 0), 0) != stack_pointer_rtx	\
-	    && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT	\
-	    && INT_8_BITS (INTVAL (XEXP (XEXP (OP, 0), 1))))))
-	 
-#define OK_FOR_T(OP) \
-   (GET_CODE (OP) == MEM					\
-    && GET_MODE (OP) == QImode					\
-    && (GET_CODE (XEXP (OP, 0)) == REG				\
-	&& REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0))			\
-	&& XEXP (OP, 0) != stack_pointer_rtx))
-
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'R' ? OK_FOR_R (OP) \
-  : (C) == 'Q' ? OK_FOR_Q (OP) \
-  : (C) == 'S' && flag_pic \
-  ? GET_CODE (OP) == UNSPEC && (XINT (OP, 1) == UNSPEC_PLT \
-				|| XINT (OP, 1) == UNSPEC_PIC) \
-  : (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF \
-  : (C) == 'T' ? OK_FOR_T (OP) \
-  : 0)
-
 /* Maximum number of registers that can appear in a valid memory address.  */
 
 #define MAX_REGS_PER_ADDRESS 2
@@ -740,7 +662,7 @@ struct cum_arg {int nbytes; };
    function record_unscaled_index_insn_codes.  */
 
 /* Accept either REG or SUBREG where a register is valid.  */
-  
+
 #define RTX_OK_FOR_BASE_P(X, strict)				\
   ((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X),		\
  					     (strict))) 	\
@@ -754,7 +676,7 @@ do							\
     if (legitimate_address_p ((MODE), (X), REG_STRICT))	\
       goto ADDR;					\
   }							\
-while (0) 
+while (0)
 
 
 /* Try machine-dependent ways of modifying an illegitimate address

gcc/config/mn10300/mn10300.md

@@ -49,6 +49,7 @@
 ])
 
 (include "predicates.md")
+(include "constraints.md")
 
 ;; ----------------------------------------------------------------------
 ;; MOVE INSTRUCTIONS
@@ -516,7 +517,7 @@
 	      return \"mov %H1,%H0\;mov %L1,%L0\";
 	    else
 	      return \"mov %L1,%L0\;mov %H1,%H0\";
-	      
+
 	  }
 	else if (GET_CODE (operands[1]) == MEM
 		 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
@@ -727,7 +728,7 @@
 	      return \"mov %H1,%H0\;mov %L1,%L0\";
 	    else
 	      return \"mov %L1,%L0\;mov %H1,%H0\";
-	      
+
 	  }
 	else if (GET_CODE (operands[1]) == MEM
 		 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
@@ -920,7 +921,7 @@
 	src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
 	src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
 	dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
-	
+
 	/* I'm not sure if this can happen or not.  Might as well be prepared
 	  and generate the best possible code if it does happen.  */
 	if (true_regnum (operands[0]) == true_regnum (operands[1]))
@@ -938,7 +939,7 @@
 	       add the other source to the destination.
 
 	       Carefully select which source to copy to the destination; a naive
-	       implementation will waste a byte when the source classes are 
+	       implementation will waste a byte when the source classes are
 	       different and the destination is an address register.  Selecting
 	       the lowest cost register copy will optimize this sequence.  */
 	    if (REGNO_REG_CLASS (true_regnum (operands[1]))
@@ -1119,7 +1120,7 @@
     return \"mul %2,%0\";
 }"
   [(set_attr "cc" "set_zn")])
-  
+
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
 	(mult:SI (match_operand:SI 1 "register_operand" "%0")
@@ -1561,7 +1562,7 @@
       else if (mask & 0xff000000)
 	mask = (mask >> 24) & 0xff;
     }
-  
+
   xoperands[0] = operands[0];
   xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
   if (GET_CODE (operands[0]) == REG)
@@ -2462,7 +2463,7 @@
   return \"\";
 }"
   [(set_attr "cc" "clobber")])
-  
+
 (define_insn "return"
   [(return)]
   "can_use_return_insn ()"

gcc/config/mn10300/predicates.md

@@ -44,7 +44,7 @@
   (match_code "symbol_ref,reg,unspec")
 {
   if (flag_pic)
-    return (EXTRA_CONSTRAINT (op, 'S') || GET_CODE (op) == REG);
+    return (satisfies_constraint_S (op) || GET_CODE (op) == REG);
 
   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
 })

gcc/genemit.c

@@ -621,7 +621,7 @@ gen_split (rtx split)
   else
     {
       printf ("extern rtx gen_split_%d (rtx, rtx *);\n", insn_code_number);
-      printf ("rtx\ngen_split_%d (rtx curr_insn ATTRIBUTE_UNUSED, rtx *operands%s)\n", 
+      printf ("rtx\ngen_split_%d (rtx curr_insn ATTRIBUTE_UNUSED, rtx *operands%s)\n",
 	      insn_code_number, unused);
     }
   printf ("{\n");
@@ -854,9 +854,10 @@ from the machine description file `md'.  */\n\n");
   printf ("#include \"resource.h\"\n");
   printf ("#include \"reload.h\"\n");
   printf ("#include \"toplev.h\"\n");
+  printf ("#include \"regs.h\"\n");
   printf ("#include \"tm-constrs.h\"\n");
-  printf ("#include \"ggc.h\"\n\n");
-  printf ("#include \"basic-block.h\"\n\n");
+  printf ("#include \"ggc.h\"\n");
+  printf ("#include \"basic-block.h\"\n");
   printf ("#include \"integrate.h\"\n\n");
   printf ("#define FAIL return (end_sequence (), _val)\n");
   printf ("#define DONE return (_val = get_insns (), end_sequence (), _val)\n\n");

gcc/genrecog.c

@@ -171,7 +171,7 @@ static int pattern_lineno;
 /* Count of errors.  */
 static int error_count;
 
-/* Predicate handling. 
+/* Predicate handling.
 
    We construct from the machine description a table mapping each
    predicate to a list of the rtl codes it can possibly match.  The
@@ -259,7 +259,7 @@ compute_predicate_codes (rtx exp, char codes[NUM_RTX_CODE])
       break;
 
     case IF_THEN_ELSE:
-      /* a ? b : c  accepts the same codes as (a & b) | (!a & c).  */ 
+      /* a ? b : c  accepts the same codes as (a & b) | (!a & c).  */
       compute_predicate_codes (XEXP (exp, 0), op0_codes);
       compute_predicate_codes (XEXP (exp, 1), op1_codes);
       compute_predicate_codes (XEXP (exp, 2), op2_codes);
@@ -295,7 +295,7 @@ compute_predicate_codes (rtx exp, char codes[NUM_RTX_CODE])
 	  {
 	    size_t n = next_code - code;
 	    int found_it = 0;
-	    
+
 	    for (i = 0; i < NUM_RTX_CODE; i++)
 	      if (!strncmp (code, GET_RTX_NAME (i), n)
 		  && GET_RTX_NAME (i)[n] == '\0')
@@ -1088,7 +1088,7 @@ add_to_sequence (rtx pattern, struct decision_head *last, const char *position,
       if (fmt[i] == 'i')
 	{
 	  gcc_assert (i < 2);
-	  
+
 	  if (!i)
 	    {
 	      test = new_decision_test (DT_elt_zero_int, &place);
@@ -2496,6 +2496,7 @@ write_header (void)
 #include \"resource.h\"\n\
 #include \"toplev.h\"\n\
 #include \"reload.h\"\n\
+#include \"regs.h\"\n\
 #include \"tm-constrs.h\"\n\
 \n");