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riscv-gcc-1
Commit 5a5d1797 by Julia Koval Committed by Kirill Yukhin
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Enable VAES support [4/5] 

gcc/
	* config/i386/i386-builtin.def (__builtin_ia32_vaesenc_v16qi,
	__builtin_ia32_vaesenc_v32qi, __builtin_ia32_vaesenc_v64qi): New.
	* config/i386/sse.md (vaesenc_<mode>): New pattern.
	* config/i386/vaesintrin.h (_mm256_aesenc_epi128, _mm512_aesenc_epi128,
	_mm_aesenc_epi128): New intrinsics.

gcc/testsuite/
	* gcc.target/i386/avx512f-aesenc-2.c: New test.
	* gcc.target/i386/avx512vl-aesenc-2.c: Ditto.
	* gcc.target/i386/avx512fvl-vaes-1.c: Handle new intrinsics.

From-SVN: r255675
parent 0ccdce5f
Showing with 125 additions and 1 deletions
gcc/ChangeLog
2017-12-15 Julia Koval <julia.koval@intel.com>
* config/i386/i386-builtin.def (__builtin_ia32_vaesenc_v16qi,
__builtin_ia32_vaesenc_v32qi, __builtin_ia32_vaesenc_v64qi): New.
* config/i386/sse.md (vaesenc_<mode>): New pattern.
* config/i386/vaesintrin.h (_mm256_aesenc_epi128, _mm512_aesenc_epi128,
_mm_aesenc_epi128): New intrinsics.
2017-12-15 Julia Koval <julia.koval@intel.com>
* config/i386/i386-builtin.def (__builtin_ia32_vaesdeclast_v16qi,
__builtin_ia32_vaesdeclast_v32qi, __builtin_ia32_vaesdeclast_v64qi): New.
* config/i386/sse.md (vaesdeclast_<mode>): New pattern.
gcc/config/i386/i386-builtin.def
......@@ -2770,6 +2770,9 @@ BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64
BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI)
BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI)
BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
BDESC_END (ARGS2, SPECIAL_ARGS2)
......
gcc/config/i386/sse.md
......@@ -176,6 +176,7 @@
;; For VAES support
UNSPEC_VAESDEC
UNSPEC_VAESDECLAST
UNSPEC_VAESENC
])
(define_c_enum "unspecv" [
......@@ -20476,3 +20477,13 @@
"TARGET_VAES"
"vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
)
(define_insn "vaesenc_<mode>"
[(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
(unspec:VI1_AVX512VL_F
[(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
(match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")]
UNSPEC_VAESENC))]
"TARGET_VAES"
"vaesenc\t{%2, %1, %0|%0, %1, %2}"
)
gcc/config/i386/vaesintrin.h
......@@ -22,6 +22,13 @@ _mm256_aesdeclast_epi128 (__m256i __A, __m256i __B)
(__v32qi) __B);
}
extern __inline __m256i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm256_aesenc_epi128 (__m256i __A, __m256i __B)
{
return (__m256i)__builtin_ia32_vaesenc_v32qi ((__v32qi) __A, (__v32qi) __B);
}
#ifdef __DISABLE_VAES__
#undef __DISABLE_VAES__
#pragma GCC pop_options
......@@ -50,6 +57,13 @@ _mm512_aesdeclast_epi128 (__m512i __A, __m512i __B)
(__v64qi) __B);
}
extern __inline __m512i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm512_aesenc_epi128 (__m512i __A, __m512i __B)
{
return (__m512i)__builtin_ia32_vaesenc_v64qi ((__v64qi) __A, (__v64qi) __B);
}
#ifdef __DISABLE_VAESF__
#undef __DISABLE_VAESF__
#pragma GCC pop_options
......@@ -76,6 +90,13 @@ _mm_aesdeclast_epi128 (__m128i __A, __m128i __B)
(__v16qi) __B);
}
extern __inline __m128i
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_aesenc_epi128 (__m128i __A, __m128i __B)
{
return (__m128i)__builtin_ia32_vaesenc_v16qi ((__v16qi) __A, (__v16qi) __B);
}
#ifdef __DISABLE_VAESVL__
#undef __DISABLE_VAESVL__
#pragma GCC pop_options
......
gcc/testsuite/ChangeLog
2017-12-12 Julia Koval <julia.koval@intel.com>
2017-12-15 Julia Koval <julia.koval@intel.com>
* gcc.target/i386/avx512f-aesenc-2.c: New test.
* gcc.target/i386/avx512vl-aesenc-2.c: Ditto.
* gcc.target/i386/avx512fvl-vaes-1.c: Handle new intrinsics.
2017-12-15 Julia Koval <julia.koval@intel.com>
* gcc.target/i386/avx512f-aesdeclast-2.c: New test.
* gcc.target/i386/avx512vl-aesdeclast-2.c
......
gcc/testsuite/gcc.target/i386/avx512f-aesenc-2.c 0 → 100644
/* { dg-do run } */
/* { dg-options "-O2 -mavx512f -mvaes" } */
/* { dg-require-effective-target avx512f } */
/* { dg-require-effective-target avx512vaes } */
#define AVX512F
#define VAES
#include "avx512f-helper.h"
#define SIZE (AVX512F_LEN / 32)
#include "avx512f-mask-type.h"
static void
CALC (unsigned int *r)
{
for (int i = 0; i < SIZE; i+=4)
{
r[i] = 0x5fb152c4;
r[i + 1] = 0x7ba60590;
r[i + 2] = 0x69e541f9;
r[i + 3] = 0xe2bd22fb;
}
}
void
TEST (void)
{
int i;
UNION_TYPE (AVX512F_LEN, i_ud) res1, src1, src2;
MASK_TYPE mask = MASK_VALUE;
unsigned int res_ref[SIZE];
for (int i = 0; i < SIZE; i+=4)
{
src1.a[i] = 0x5d53475d;
src1.a[i + 1] = 0x63746f72;
src1.a[i + 2] = 0x73745665;
src1.a[i + 3] = 0x7b5b5465;
src2.a[i] = 0x726f6e5d;
src2.a[i + 1] = 0x5b477565;
src2.a[i + 2] = 0x68617929;
src2.a[i + 3] = 0x48692853;
}
CALC (res_ref);
res1.x = INTRINSIC (_aesenc_epi128) (src2.x, src1.x);
if (UNION_CHECK (AVX512F_LEN, i_ud) (res1, res_ref))
abort ();
}
gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c
......@@ -2,12 +2,15 @@
/* { dg-options "-mvaes -mavx512f -mavx512vl -O2" } */
/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesdeclast\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\{\n\]*%zmm\[0-9\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesenc\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesdeclast\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesenc\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesdeclast\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesenc\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
......@@ -20,10 +23,13 @@ avx512f_test (void)
{
x = _mm512_aesdec_epi128 (x, y);
x = _mm512_aesdeclast_epi128 (x, y);
x = _mm512_aesenc_epi128 (x, y);
x256 = _mm256_aesdec_epi128 (x256, y256);
x256 = _mm256_aesdeclast_epi128 (x256, y256);
x256 = _mm256_aesenc_epi128 (x256, y256);
x128 = _mm_aesdec_epi128 (x128, y128);
x128 = _mm_aesdeclast_epi128 (x128, y128);
x128 = _mm_aesenc_epi128 (x128, y128);
}
gcc/testsuite/gcc.target/i386/avx512vl-aesenc-2.c 0 → 100644
/* { dg-do run } */
/* { dg-options "-O2 -mavx512bw -mavx512vl -mvaes" } */
/* { dg-require-effective-target avx512vl } */
/* { dg-require-effective-target avx512bw } */
/* { dg-require-effective-target avx512vaes } */
#define AVX512VL
#define AVX512F_LEN 256
#define AVX512F_LEN_HALF 128
#include "avx512f-aesenc-2.c"
#undef AVX512F_LEN
#undef AVX512F_LEN_HALF
#define AVX512F_LEN 128
#define AVX512F_LEN_HALF 128
#include "avx512f-aesenc-2.c"
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