rs6000.c: Include params.h

        * config/rs6000/rs6000.c: Include params.h
        (optimization_options): Set max-grow-copy-bb-insns default to 16.
        (bdesc_2arg): Delete vpkuhss and vpkuwss.
        * config/rs6000/altivec.md (UNSPEC_VPKUHSS): Delete.
        (UNSPEC_VPKUWSS): Delete.
        (altivec_vpkuhss): Delete.
        (altivec_vpkuwss): Delete.
        * config/rs6000/rs6000.md (plus_eqsi): Remove optimize_size from
        final condition.
        (neg_eq0<mode>): Remove final condition.
        (neg_eq<mode>): Remove condition and split-condition.

From-SVN: r106479

gcc/config/rs6000/altivec.md

@@ -57,9 +57,7 @@
    (UNSPEC_VPKUHUM       93)
    (UNSPEC_VPKUWUM       94)
    (UNSPEC_VPKPX         95)
-   (UNSPEC_VPKUHSS       96)
    (UNSPEC_VPKSHSS       97)
-   (UNSPEC_VPKUWSS       98)
    (UNSPEC_VPKSWSS       99)
    (UNSPEC_VPKUHUS      100)
    (UNSPEC_VPKSHUS      101)
@@ -1105,16 +1103,6 @@
   "vpkpx %0,%1,%2"
   [(set_attr "type" "vecperm")])
 
-(define_insn "altivec_vpkuhss"
-  [(set (match_operand:V16QI 0 "register_operand" "=v")
-        (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-                       (match_operand:V8HI 2 "register_operand" "v")]
-		      UNSPEC_VPKUHSS))
-   (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-  "TARGET_ALTIVEC"
-  "vpkuhss %0,%1,%2"
-  [(set_attr "type" "vecperm")])
-
 (define_insn "altivec_vpkshss"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
@@ -1125,16 +1113,6 @@
   "vpkshss %0,%1,%2"
   [(set_attr "type" "vecperm")])
 
-(define_insn "altivec_vpkuwss"
-  [(set (match_operand:V8HI 0 "register_operand" "=v")
-        (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-                      (match_operand:V4SI 2 "register_operand" "v")]
-		     UNSPEC_VPKUWSS))
-   (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-  "TARGET_ALTIVEC"
-  "vpkuwss %0,%1,%2"
-  [(set_attr "type" "vecperm")])
-
 (define_insn "altivec_vpkswss"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")

gcc/config/rs6000/rs6000.c

@@ -54,6 +54,7 @@
 #include "sched-int.h"
 #include "tree-gimple.h"
 #include "intl.h"
+#include "params.h"
 #if TARGET_XCOFF
 #include "xcoffout.h"  /* get declarations of xcoff_*_section_name */
 #endif
@@ -1573,6 +1574,9 @@ optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
     /* The Darwin libraries never set errno, so we might as well
        avoid calling them when that's the only reason we would.  */
     flag_errno_math = 0;
+
+  /* Double growth factor to counter reduced min jump length.  */
+  set_param_value ("max-grow-copy-bb-insns", 16);
 }
 
 /* Implement TARGET_HANDLE_OPTION.  */
@@ -5971,9 +5975,7 @@ static struct builtin_description bdesc_2arg[] =
   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
   { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
   { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
-  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
   { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
   { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },

gcc/config/rs6000/rs6000.md

@@ -11264,7 +11264,7 @@
 	(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 			(match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
 		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
-  "TARGET_32BIT && optimize_size"
+  "TARGET_32BIT"
   "@
    xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
    {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
@@ -11364,7 +11364,7 @@
   [(set (match_operand:P 0 "gpc_reg_operand" "=r")
 	(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
 		     (const_int 0))))]
-  "optimize_size || TARGET_POWER"
+  ""
   "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
   [(set_attr "type" "two")
    (set_attr "length" "8")])
@@ -11373,9 +11373,9 @@
   [(set (match_operand:P 0 "gpc_reg_operand" "=r")
 	(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
 		     (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
-  "optimize_size || TARGET_POWER"
+  ""
   "#"
-  "optimize_size || TARGET_POWER"
+  ""
   [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
   {
     if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)