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Commit 59823ba4 by David S. Miller Committed by David S. Miller
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sparc.md (type attribute): Add new insn types fpa, fpm_pack, fgm_mul, fgm_pdist,… 

sparc.md (type attribute): Add new insn types fpa, fpm_pack, fgm_mul, fgm_pdist, and fgm_cmp for VIS.

	* config/sparc/sparc.md (type attribute): Add new insn types
	fpa, fpm_pack, fgm_mul, fgm_pdist, and fgm_cmp for VIS.
	(patterns emitting VIS insns): Use them.
	* config/sparc/ultra1_2.md: Add VIS scheduling rules.
	* config/sparc/ultra3.md: Likewise.

From-SVN: r72697
parent e006ced2
Showing with 108 additions and 28 deletions
gcc/ChangeLog
2003-10-20 David S. Miller <davem@redhat.com>
* config/sparc/sparc.md (type attribute): Add new insn types
fpa, fpm_pack, fgm_mul, fgm_pdist, and fgm_cmp for VIS.
(patterns emitting VIS insns): Use them.
* config/sparc/ultra1_2.md: Add VIS scheduling rules.
* config/sparc/ultra3.md: Likewise.
2003-10-20 Falk Hueffner <falk@debian.org> 2003-10-20 Falk Hueffner <falk@debian.org>
PR target/12654 PR target/12654
......
gcc/config/sparc/sparc.md
...@@ -106,6 +106,7 @@ ...@@ -106,6 +106,7 @@
fpcmp, fpcmp,
fpmul,fpdivs,fpdivd, fpmul,fpdivs,fpdivd,
fpsqrts,fpsqrtd, fpsqrts,fpsqrtd,
fga,fgm_pack,fgm_mul,fgm_pdist,fgm_cmp,
cmove, cmove,
ialuX, ialuX,
multi,flushw,iflush,trap" multi,flushw,iflush,trap"
...@@ -1920,7 +1921,7 @@ ...@@ -1920,7 +1921,7 @@
st\t%r1, %0 st\t%r1, %0
st\t%1, %0 st\t%1, %0
fzeros\t%0" fzeros\t%0"
[(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove")]) [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fga")])
(define_insn "*movsi_lo_sum" (define_insn "*movsi_lo_sum"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -2192,7 +2193,7 @@ ...@@ -2192,7 +2193,7 @@
ldd\t%1, %0 ldd\t%1, %0
std\t%1, %0 std\t%1, %0
fzero\t%0" fzero\t%0"
[(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fpmove") [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fga")
(set_attr "fptype" "*,*,*,*,*,double,*,*,double")]) (set_attr "fptype" "*,*,*,*,*,double,*,*,double")])
(define_expand "movdi_pic_label_ref" (define_expand "movdi_pic_label_ref"
...@@ -2640,7 +2641,7 @@ ...@@ -2640,7 +2641,7 @@
abort(); abort();
} }
} }
[(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")]) [(set_attr "type" "fpmove,fga,*,*,*,*,load,fpload,fpstore,store")])
;; Exactly the same as above, except that all `f' cases are deleted. ;; Exactly the same as above, except that all `f' cases are deleted.
;; This is necessary to prevent reload from ever trying to use a `f' reg ;; This is necessary to prevent reload from ever trying to use a `f' reg
...@@ -2957,7 +2958,7 @@ ...@@ -2957,7 +2958,7 @@
# #
# #
#" #"
[(set_attr "type" "fpmove,fpmove,load,store,store,load,store,*,*,*") [(set_attr "type" "fga,fpmove,load,store,store,load,store,*,*,*")
(set_attr "length" "*,*,*,*,*,*,*,2,2,2") (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
(set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")]) (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
...@@ -3004,7 +3005,7 @@ ...@@ -3004,7 +3005,7 @@
ldx\t%1, %0 ldx\t%1, %0
stx\t%r1, %0 stx\t%r1, %0
#" #"
[(set_attr "type" "fpmove,fpmove,load,store,*,load,store,*") [(set_attr "type" "fga,fpmove,load,store,*,load,store,*")
(set_attr "length" "*,*,*,*,*,*,*,2") (set_attr "length" "*,*,*,*,*,*,*,2")
(set_attr "fptype" "double,double,*,*,*,*,*,*")]) (set_attr "fptype" "double,double,*,*,*,*,*,*")])
...@@ -4976,7 +4977,7 @@ ...@@ -4976,7 +4977,7 @@
add\t%1, %2, %0 add\t%1, %2, %0
sub\t%1, -%2, %0 sub\t%1, -%2, %0
fpadd32s\t%1, %2, %0" fpadd32s\t%1, %2, %0"
[(set_attr "type" "*,*,fp")]) [(set_attr "type" "*,*,fga")])
(define_insn "*cmp_cc_plus" (define_insn "*cmp_cc_plus"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -5132,7 +5133,7 @@ ...@@ -5132,7 +5133,7 @@
sub\t%1, %2, %0 sub\t%1, %2, %0
add\t%1, -%2, %0 add\t%1, -%2, %0
fpsub32s\t%1, %2, %0" fpsub32s\t%1, %2, %0"
[(set_attr "type" "*,*,fp")]) [(set_attr "type" "*,*,fga")])
(define_insn "*cmp_minus_cc" (define_insn "*cmp_minus_cc"
[(set (reg:CC_NOOV 100) [(set (reg:CC_NOOV 100)
...@@ -5856,7 +5857,7 @@ ...@@ -5856,7 +5857,7 @@
"@ "@
# #
fand\t%1, %2, %0" fand\t%1, %2, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "length" "2,*") (set_attr "length" "2,*")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
...@@ -5868,7 +5869,7 @@ ...@@ -5868,7 +5869,7 @@
"@ "@
and\t%1, %2, %0 and\t%1, %2, %0
fand\t%1, %2, %0" fand\t%1, %2, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
(define_insn "andsi3" (define_insn "andsi3"
...@@ -5879,7 +5880,7 @@ ...@@ -5879,7 +5880,7 @@
"@ "@
and\t%1, %2, %0 and\t%1, %2, %0
fands\t%1, %2, %0" fands\t%1, %2, %0"
[(set_attr "type" "*,fp")]) [(set_attr "type" "*,fga")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -5951,7 +5952,7 @@ ...@@ -5951,7 +5952,7 @@
operands[6] = gen_lowpart (SImode, operands[0]); operands[6] = gen_lowpart (SImode, operands[0]);
operands[7] = gen_lowpart (SImode, operands[1]); operands[7] = gen_lowpart (SImode, operands[1]);
operands[8] = gen_lowpart (SImode, operands[2]);" operands[8] = gen_lowpart (SImode, operands[2]);"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "length" "2,*") (set_attr "length" "2,*")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
...@@ -5963,7 +5964,7 @@ ...@@ -5963,7 +5964,7 @@
"@ "@
andn\t%2, %1, %0 andn\t%2, %1, %0
fandnot1\t%1, %2, %0" fandnot1\t%1, %2, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
(define_insn "*and_not_si" (define_insn "*and_not_si"
...@@ -5974,7 +5975,7 @@ ...@@ -5974,7 +5975,7 @@
"@ "@
andn\t%2, %1, %0 andn\t%2, %1, %0
fandnot1s\t%1, %2, %0" fandnot1s\t%1, %2, %0"
[(set_attr "type" "*,fp")]) [(set_attr "type" "*,fga")])
(define_expand "iordi3" (define_expand "iordi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -5991,7 +5992,7 @@ ...@@ -5991,7 +5992,7 @@
"@ "@
# #
for\t%1, %2, %0" for\t%1, %2, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "length" "2,*") (set_attr "length" "2,*")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
...@@ -6003,7 +6004,7 @@ ...@@ -6003,7 +6004,7 @@
"@ "@
or\t%1, %2, %0 or\t%1, %2, %0
for\t%1, %2, %0" for\t%1, %2, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
(define_insn "iorsi3" (define_insn "iorsi3"
...@@ -6014,7 +6015,7 @@ ...@@ -6014,7 +6015,7 @@
"@ "@
or\t%1, %2, %0 or\t%1, %2, %0
fors\t%1, %2, %0" fors\t%1, %2, %0"
[(set_attr "type" "*,fp")]) [(set_attr "type" "*,fga")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -6052,7 +6053,7 @@ ...@@ -6052,7 +6053,7 @@
operands[6] = gen_lowpart (SImode, operands[0]); operands[6] = gen_lowpart (SImode, operands[0]);
operands[7] = gen_lowpart (SImode, operands[1]); operands[7] = gen_lowpart (SImode, operands[1]);
operands[8] = gen_lowpart (SImode, operands[2]);" operands[8] = gen_lowpart (SImode, operands[2]);"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "length" "2,*") (set_attr "length" "2,*")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
...@@ -6064,7 +6065,7 @@ ...@@ -6064,7 +6065,7 @@
"@ "@
orn\t%2, %1, %0 orn\t%2, %1, %0
fornot1\t%1, %2, %0" fornot1\t%1, %2, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
(define_insn "*or_not_si" (define_insn "*or_not_si"
...@@ -6075,7 +6076,7 @@ ...@@ -6075,7 +6076,7 @@
"@ "@
orn\t%2, %1, %0 orn\t%2, %1, %0
fornot1s\t%1, %2, %0" fornot1s\t%1, %2, %0"
[(set_attr "type" "*,fp")]) [(set_attr "type" "*,fga")])
(define_expand "xordi3" (define_expand "xordi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -6092,7 +6093,7 @@ ...@@ -6092,7 +6093,7 @@
"@ "@
# #
fxor\t%1, %2, %0" fxor\t%1, %2, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "length" "2,*") (set_attr "length" "2,*")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
...@@ -6104,7 +6105,7 @@ ...@@ -6104,7 +6105,7 @@
"@ "@
xor\t%r1, %2, %0 xor\t%r1, %2, %0
fxor\t%1, %2, %0" fxor\t%1, %2, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
(define_insn "*xordi3_sp64_dbl" (define_insn "*xordi3_sp64_dbl"
...@@ -6123,7 +6124,7 @@ ...@@ -6123,7 +6124,7 @@
"@ "@
xor\t%r1, %2, %0 xor\t%r1, %2, %0
fxors\t%1, %2, %0" fxors\t%1, %2, %0"
[(set_attr "type" "*,fp")]) [(set_attr "type" "*,fga")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -6177,7 +6178,7 @@ ...@@ -6177,7 +6178,7 @@
operands[6] = gen_lowpart (SImode, operands[0]); operands[6] = gen_lowpart (SImode, operands[0]);
operands[7] = gen_lowpart (SImode, operands[1]); operands[7] = gen_lowpart (SImode, operands[1]);
operands[8] = gen_lowpart (SImode, operands[2]);" operands[8] = gen_lowpart (SImode, operands[2]);"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "length" "2,*") (set_attr "length" "2,*")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
...@@ -6189,7 +6190,7 @@ ...@@ -6189,7 +6190,7 @@
"@ "@
xnor\t%r1, %2, %0 xnor\t%r1, %2, %0
fxnor\t%1, %2, %0" fxnor\t%1, %2, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
(define_insn "*xor_not_si" (define_insn "*xor_not_si"
...@@ -6200,7 +6201,7 @@ ...@@ -6200,7 +6201,7 @@
"@ "@
xnor\t%r1, %2, %0 xnor\t%r1, %2, %0
fxnors\t%1, %2, %0" fxnors\t%1, %2, %0"
[(set_attr "type" "*,fp")]) [(set_attr "type" "*,fga")])
;; These correspond to the above in the case where we also (or only) ;; These correspond to the above in the case where we also (or only)
;; want to set the condition code. ;; want to set the condition code.
...@@ -6463,7 +6464,7 @@ ...@@ -6463,7 +6464,7 @@
operands[3] = gen_highpart (SImode, operands[1]); operands[3] = gen_highpart (SImode, operands[1]);
operands[4] = gen_lowpart (SImode, operands[0]); operands[4] = gen_lowpart (SImode, operands[0]);
operands[5] = gen_lowpart (SImode, operands[1]);" operands[5] = gen_lowpart (SImode, operands[1]);"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "length" "2,*") (set_attr "length" "2,*")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
...@@ -6474,7 +6475,7 @@ ...@@ -6474,7 +6475,7 @@
"@ "@
xnor\t%%g0, %1, %0 xnor\t%%g0, %1, %0
fnot1\t%1, %0" fnot1\t%1, %0"
[(set_attr "type" "*,fp") [(set_attr "type" "*,fga")
(set_attr "fptype" "double")]) (set_attr "fptype" "double")])
(define_insn "one_cmplsi2" (define_insn "one_cmplsi2"
...@@ -6484,7 +6485,7 @@ ...@@ -6484,7 +6485,7 @@
"@ "@
xnor\t%%g0, %1, %0 xnor\t%%g0, %1, %0
fnot1s\t%1, %0" fnot1s\t%1, %0"
[(set_attr "type" "*,fp")]) [(set_attr "type" "*,fga")])
(define_insn "*cmp_cc_not" (define_insn "*cmp_cc_not"
[(set (reg:CC 100) [(set (reg:CC 100)
......
gcc/config/sparc/ultra1_2.md
...@@ -250,3 +250,53 @@ ...@@ -250,3 +250,53 @@
;; An integer branch may execute in the same cycle as the compare ;; An integer branch may execute in the same cycle as the compare
;; creating the condition codes. ;; creating the condition codes.
(define_bypass 0 "us1_simple_ieu1" "us1_branch") (define_bypass 0 "us1_simple_ieu1" "us1_branch")
;; VIS scheduling
(define_insn_reservation "us1_fga_single"
2
(and (and
(eq_attr "cpu" "ultrasparc")
(eq_attr "type" "fga"))
(eq_attr "fptype" "single"))
"us1_fpa + us1_fp_single + us1_slotany, nothing")
(define_bypass 1 "us1_fga_single" "us1_fga_single")
(define_insn_reservation "us1_fga_double"
2
(and (and
(eq_attr "cpu" "ultrasparc")
(eq_attr "type" "fga"))
(eq_attr "fptype" "double"))
"us1_fpa + us1_fp_double + us1_slotany, nothing")
(define_bypass 1 "us1_fga_double" "us1_fga_double")
(define_insn_reservation "us1_fgm_single"
4
(and (and
(eq_attr "cpu" "ultrasparc")
(eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp"))
(eq_attr "fptype" "single"))
"us1_fpm + us1_fp_single + us1_slotany, nothing*3")
(define_bypass 3 "us1_fgm_single" "us1_fga_single")
(define_insn_reservation "us1_fgm_double"
4
(and (and
(eq_attr "cpu" "ultrasparc")
(eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp"))
(eq_attr "fptype" "double"))
"us1_fpm + us1_fp_double + us1_slotany, nothing*3")
(define_bypass 3 "us1_fgm_double" "us1_fga_double")
(define_insn_reservation "us1_pdist"
4
(and (eq_attr "cpu" "ultrasparc")
(eq_attr "type" "fgm_pdist"))
"us1_fpm + us1_fp_double + us1_slotany, nothing*3")
(define_bypass 3 "us1_pdist" "us1_fga_double,us1_fga_single")
(define_bypass 1 "us1_pdist" "us1_pdist")
gcc/config/sparc/ultra3.md
...@@ -167,3 +167,24 @@ ...@@ -167,3 +167,24 @@
;; If FMOVfcc is user of FPCMP, latency is only 1 cycle. ;; If FMOVfcc is user of FPCMP, latency is only 1 cycle.
(define_bypass 1 "us3_fpcmp" "us3_fcmov") (define_bypass 1 "us3_fpcmp" "us3_fcmov")
;; VIS scheduling
(define_insn_reservation "us3_fga"
3
(and (eq_attr "cpu" "ultrasparc3")
(eq_attr "type" "fga"))
"us3_fpa + us3_slotany, nothing*2")
(define_insn_reservation "us3_fgm"
4
(and (eq_attr "cpu" "ultrasparc3")
(eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp"))
"us3_fpm + us3_slotany, nothing*3")
(define_insn_reservation "us3_pdist"
4
(and (eq_attr "cpu" "ultrasparc3")
(eq_attr "type" "fgm_pdist"))
"us3_fpm + us3_slotany, nothing*3")
(define_bypass 1 "us3_pdist" "us3_pdist")
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