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Commit 594726e4 by James Greenhalgh Committed by James Greenhalgh
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[Patch ARM] Add "type" attribute to Everything! 

gcc/
	* config/arm/types.md: Add "no_insn", "multiple" and "untyped"
	types.
	* config/arm/arm-fixed.md: Add type attribute to all insn
	patterns.
	* config/arm/vfp.md: Add type attribute to all insn patterns.
	* config/arm/arm.md: Add type attribute to all insn patterns.
	* config/arm/thumb2.md: Add type attribute to all insn patterns.
	* config/arm/arm1020e.md: Update with new attributes.
	* config/arm/arm1026ejs.md: Update with new attributes.
	* config/arm/arm1136jfs.md: Update with new attributes.
	* config/arm/arm926ejs.md: Update with new attributes.
	* config/arm/cortex-a15.md: Update with new attributes.
	* config/arm/cortex-a5.md: Update with new attributes.
	* config/arm/cortex-a53.md: Update with new attributes.
	* config/arm/cortex-a7.md: Update with new attributes.
	* config/arm/cortex-a8.md: Update with new attributes.
	* config/arm/cortex-a9.md: Update with new attributes.
	* config/arm/cortex-m4.md: Update with new attributes.
	* config/arm/cortex-r4.md: Update with new attributes.
	* config/arm/fa526.md: Update with new attributes.
	* config/arm/fa606te.md: Update with new attributes.
	* config/arm/fa626te.md: Update with new attributes.
	* config/arm/fa726te.md: Update with new attributes.

From-SVN: r202323
parent 1c83b673
Showing with 410 additions and 72 deletions
gcc/ChangeLog
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com> 2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/types.md: Add "no_insn", "multiple" and "untyped"
types.
* config/arm/arm-fixed.md: Add type attribute to all insn
patterns.
(add<mode>3): Add type attribute.
(add<mode>3): Likewise.
(usadd<mode>3): Likewise.
(ssadd<mode>3): Likewise.
(sub<mode>3): Likewise.
(sub<mode>3): Likewise.
(ussub<mode>3): Likewise.
(sssub<mode>3): Likewise.
(ssmulsa3): Likewise.
(usmulusa3): Likewise.
(arm_usatsihi): Likewise.
* config/arm/vfp.md
(*movdi_vfp): Add types for all instructions.
(*movdi_vfp_cortexa8): Likewise.
(*movhf_vfp_neon): Likewise.
(*movhf_vfp): Likewise.
(*movdf_vfp): Likewise.
(*thumb2_movdf_vfp): Likewise.
(*thumb2_movdfcc_vfp): Likewise.
* config/arm/arm.md: Add type attribute to all insn patterns.
(*thumb1_adddi3): Add type attribute.
(*arm_adddi3): Likewise.
(*adddi_sesidi_di): Likewise.
(*adddi_zesidi_di): Likewise.
(*thumb1_addsi3): Likewise.
(addsi3_compare0): Likewise.
(*addsi3_compare0_scratch): Likewise.
(*compare_negsi_si): Likewise.
(cmpsi2_addneg): Likewise.
(*addsi3_carryin_<optab>): Likewise.
(*addsi3_carryin_alt2_<optab>): Likewise.
(*addsi3_carryin_clobercc_<optab>): Likewise.
(*subsi3_carryin): Likewise.
(*subsi3_carryin_const): Likewise.
(*subsi3_carryin_compare): Likewise.
(*subsi3_carryin_compare_const): Likewise.
(*arm_subdi3): Likewise.
(*thumb_subdi3): Likewise.
(*subdi_di_zesidi): Likewise.
(*subdi_di_sesidi): Likewise.
(*subdi_zesidi_di): Likewise.
(*subdi_sesidi_di): Likewise.
(*subdi_zesidi_ze): Likewise.
(thumb1_subsi3_insn): Likewise.
(*arm_subsi3_insn): Likewise.
(*anddi3_insn): Likewise.
(*anddi_zesidi_di): Likewise.
(*anddi_sesdi_di): Likewise.
(*ne_zeroextracts): Likewise.
(*ne_zeroextracts): Likewise.
(*ite_ne_zeroextr): Likewise.
(*ite_ne_zeroextr): Likewise.
(*anddi_notdi_di): Likewise.
(*anddi_notzesidi): Likewise.
(*anddi_notsesidi): Likewise.
(andsi_notsi_si): Likewise.
(thumb1_bicsi3): Likewise.
(*iordi3_insn): Likewise.
(*iordi_zesidi_di): Likewise.
(*iordi_sesidi_di): Likewise.
(*thumb1_iorsi3_insn): Likewise.
(*xordi3_insn): Likewise.
(*xordi_zesidi_di): Likewise.
(*xordi_sesidi_di): Likewise.
(*arm_xorsi3): Likewise.
(*andsi_iorsi3_no): Likewise.
(*smax_0): Likewise.
(*smax_m1): Likewise.
(*arm_smax_insn): Likewise.
(*smin_0): Likewise.
(*arm_smin_insn): Likewise.
(*arm_umaxsi3): Likewise.
(*arm_uminsi3): Likewise.
(*minmax_arithsi): Likewise.
(*minmax_arithsi_): Likewise.
(*satsi_<SAT:code>): Likewise.
(arm_ashldi3_1bit): Likewise.
(arm_ashrdi3_1bit): Likewise.
(arm_lshrdi3_1bit): Likewise.
(*arm_negdi2): Likewise.
(*thumb1_negdi2): Likewise.
(*arm_negsi2): Likewise.
(*thumb1_negsi2): Likewise.
(*negdi_extendsid): Likewise.
(*negdi_zero_extend): Likewise.
(*arm_abssi2): Likewise.
(*thumb1_abssi2): Likewise.
(*arm_neg_abssi2): Likewise.
(*thumb1_neg_abss): Likewise.
(one_cmpldi2): Likewise.
(extend<mode>di2): Likewise.
(*compareqi_eq0): Likewise.
(*arm_extendhisi2addsi): Likewise.
(*arm_movdi): Likewise.
(*thumb1_movdi_insn): Likewise.
(*arm_movt): Likewise.
(*thumb1_movsi_insn): Likewise.
(pic_add_dot_plus_four): Likewise.
(pic_add_dot_plus_eight): Likewise.
(tls_load_dot_plus_eight): Likewise.
(*thumb1_movhi_insn): Likewise.
(*thumb1_movsf_insn): Likewise.
(*movdf_soft_insn): Likewise.
(*thumb_movdf_insn): Likewise.
(cbranchsi4_insn): Likewise.
(cbranchsi4_scratch): Likewise.
(*negated_cbranchsi4): Likewise.
(*tbit_cbranch): Likewise.
(*tlobits_cbranch): Likewise.
(*tstsi3_cbranch): Likewise.
(*cbranchne_decr1): Likewise.
(*addsi3_cbranch): Likewise.
(*addsi3_cbranch_scratch): Likewise.
(*arm_cmpdi_insn): Likewise.
(*arm_cmpdi_unsig): Likewise.
(*arm_cmpdi_zero): Likewise.
(*thumb_cmpdi_zero): Likewise.
(*deleted_compare): Likewise.
(*mov_scc): Likewise.
(*mov_negscc): Likewise.
(*mov_notscc): Likewise.
(*cstoresi_eq0_thumb1_insn): Likewise.
(cstoresi_nltu_thumb1): Likewise.
(cstoresi_ltu_thu): Likewise.
(thumb1_addsi3_addgeu): Likewise.
(*arm_jump): Likewise.
(*thumb_jump): Likewise.
(*check_arch2): Likewise.
(arm_casesi_internal): Likewise.
(thumb1_casesi_dispatch): Likewise.
(*arm_indirect_jump): Likewise.
(*thumb1_indirect_jump): Likewise.
(nop): Likewise.
(*and_scc): Likewise.
(*ior_scc): Likewise.
(*compare_scc): Likewise.
(*cond_move): Likewise.
(*cond_arith): Likewise.
(*cond_sub): Likewise.
(*cmp_ite0): Likewise.
(*cmp_ite1): Likewise.
(*cmp_and): Likewise.
(*cmp_ior): Likewise.
(*ior_scc_scc): Likewise.
(*ior_scc_scc_cmp): Likewise.
(*and_scc_scc): Likewise.
(*and_scc_scc_cmp): Likewise.
(*and_scc_scc_nod): Likewise.
(*negscc): Likewise.
(movcond_addsi): Likewise.
(movcond): Likewise.
(*ifcompare_plus_move): Likewise.
(*if_plus_move): Likewise.
(*ifcompare_move_plus): Likewise.
(*if_move_plus): Likewise.
(*ifcompare_arith_arith): Likewise.
(*if_arith_arith): Likewise.
(*ifcompare_arith_move): Likewise.
(*if_arith_move): Likewise.
(*ifcompare_move_arith): Likewise.
(*if_move_arith): Likewise.
(*ifcompare_move_not): Likewise.
(*if_move_not): Likewise.
(*ifcompare_not_move): Likewise.
(*if_not_move): Likewise.
(*ifcompare_shift_move): Likewise.
(*if_shift_move): Likewise.
(*ifcompare_move_shift): Likewise.
(*if_move_shift): Likewise.
(*ifcompare_shift_shift): Likewise.
(*ifcompare_not_arith): Likewise.
(*ifcompare_arith_not): Likewise.
(*if_arith_not): Likewise.
(*ifcompare_neg_move): Likewise.
(*if_neg_move): Likewise.
(*ifcompare_move_neg): Likewise.
(*if_move_neg): Likewise.
(prologue_thumb1_interwork): Likewise.
(*cond_move_not): Likewise.
(*sign_extract_onebit): Likewise.
(*not_signextract_onebit): Likewise.
(stack_tie): Likewise.
(align_4): Likewise.
(align_8): Likewise.
(consttable_end): Likewise.
(consttable_1): Likewise.
(consttable_2): Likewise.
(consttable_4): Likewise.
(consttable_8): Likewise.
(consttable_16): Likewise.
(*thumb1_tablejump): Likewise.
(prefetch): Likewise.
(force_register_use): Likewise.
(thumb_eh_return): Likewise.
(load_tp_hard): Likewise.
(load_tp_soft): Likewise.
(tlscall): Likewise.
(*arm_movtas_ze): Likewise.
(*arm_rev): Likewise.
(*arm_revsh): Likewise.
(*arm_rev16): Likewise.
* config/arm/thumb2.md
(*thumb2_smaxsi3): Likewise.
(*thumb2_sminsi3): Likewise.
(*thumb32_umaxsi3): Likewise.
(*thumb2_uminsi3): Likewise.
(*thumb2_negdi2): Likewise.
(*thumb2_abssi2): Likewise.
(*thumb2_neg_abss): Likewise.
(*thumb2_movsi_insn): Likewise.
(tls_load_dot_plus_four): Likewise.
(*thumb2_movhi_insn): Likewise.
(*thumb2_mov_scc): Likewise.
(*thumb2_mov_negs): Likewise.
(*thumb2_mov_negs): Likewise.
(*thumb2_mov_nots): Likewise.
(*thumb2_mov_nots): Likewise.
(*thumb2_movsicc_): Likewise.
(*thumb2_movsfcc_soft_insn): Likewise.
(*thumb2_indirect_jump): Likewise.
(*thumb2_and_scc): Likewise.
(*thumb2_ior_scc): Likewise.
(*thumb2_ior_scc_strict_it): Likewise.
(*thumb2_cond_move): Likewise.
(*thumb2_cond_arith): Likewise.
(*thumb2_cond_ari): Likewise.
(*thumb2_cond_sub): Likewise.
(*thumb2_negscc): Likewise.
(*thumb2_movcond): Likewise.
(thumb2_casesi_internal): Likewise.
(thumb2_casesi_internal_pic): Likewise.
(*thumb2_alusi3_short): Likewise.
(*thumb2_mov<mode>_shortim): Likewise.
(*thumb2_addsi_short): Likewise.
(*thumb2_subsi_short): Likewise.
(thumb2_addsi3_compare0): Likewise.
(*thumb2_cbz): Likewise.
(*thumb2_cbnz): Likewise.
(*thumb2_one_cmplsi2_short): Likewise.
(*thumb2_negsi2_short): Likewise.
(*orsi_notsi_si): Likewise.
* config/arm/arm1020e.md: Update with new attributes.
* config/arm/arm1026ejs.md: Update with new attributes.
* config/arm/arm1136jfs.md: Update with new attributes.
* config/arm/arm926ejs.md: Update with new attributes.
* config/arm/cortex-a15.md: Update with new attributes.
* config/arm/cortex-a5.md: Update with new attributes.
* config/arm/cortex-a53.md: Update with new attributes.
* config/arm/cortex-a7.md: Update with new attributes.
* config/arm/cortex-a8.md: Update with new attributes.
* config/arm/cortex-a9.md: Update with new attributes.
* config/arm/cortex-m4.md: Update with new attributes.
* config/arm/cortex-r4.md: Update with new attributes.
* config/arm/fa526.md: Update with new attributes.
* config/arm/fa606te.md: Update with new attributes.
* config/arm/fa626te.md: Update with new attributes.
* config/arm/fa726te.md: Update with new attributes.
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd.md * config/aarch64/aarch64-simd.md
(aarch64_sqdml<SBINQOPS:as>l_n<mode>_internal): Use (aarch64_sqdml<SBINQOPS:as>l_n<mode>_internal): Use
<vwx> iterator to ensure correct register choice. <vwx> iterator to ensure correct register choice.
......
gcc/config/arm/arm-fixed.md
...@@ -25,7 +25,8 @@ ...@@ -25,7 +25,8 @@
"TARGET_32BIT" "TARGET_32BIT"
"add%?\\t%0, %1, %2" "add%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no")]) (set_attr "predicable_short_it" "yes,no")
(set_attr "type" "alu_reg")])
(define_insn "add<mode>3" (define_insn "add<mode>3"
[(set (match_operand:ADDSUB 0 "s_register_operand" "=r") [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
...@@ -34,7 +35,8 @@ ...@@ -34,7 +35,8 @@
"TARGET_INT_SIMD" "TARGET_INT_SIMD"
"sadd<qaddsub_suf>%?\\t%0, %1, %2" "sadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]) (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")])
(define_insn "usadd<mode>3" (define_insn "usadd<mode>3"
[(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
...@@ -43,7 +45,8 @@ ...@@ -43,7 +45,8 @@
"TARGET_INT_SIMD" "TARGET_INT_SIMD"
"uqadd<qaddsub_suf>%?\\t%0, %1, %2" "uqadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]) (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")])
(define_insn "ssadd<mode>3" (define_insn "ssadd<mode>3"
[(set (match_operand:QADDSUB 0 "s_register_operand" "=r") [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
...@@ -52,7 +55,8 @@ ...@@ -52,7 +55,8 @@
"TARGET_INT_SIMD" "TARGET_INT_SIMD"
"qadd<qaddsub_suf>%?\\t%0, %1, %2" "qadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]) (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")])
(define_insn "sub<mode>3" (define_insn "sub<mode>3"
[(set (match_operand:FIXED 0 "s_register_operand" "=l,r") [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
...@@ -61,7 +65,8 @@ ...@@ -61,7 +65,8 @@
"TARGET_32BIT" "TARGET_32BIT"
"sub%?\\t%0, %1, %2" "sub%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no")]) (set_attr "predicable_short_it" "yes,no")
(set_attr "type" "alu_reg")])
(define_insn "sub<mode>3" (define_insn "sub<mode>3"
[(set (match_operand:ADDSUB 0 "s_register_operand" "=r") [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
...@@ -70,7 +75,8 @@ ...@@ -70,7 +75,8 @@
"TARGET_INT_SIMD" "TARGET_INT_SIMD"
"ssub<qaddsub_suf>%?\\t%0, %1, %2" "ssub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]) (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")])
(define_insn "ussub<mode>3" (define_insn "ussub<mode>3"
[(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
...@@ -80,7 +86,8 @@ ...@@ -80,7 +86,8 @@
"TARGET_INT_SIMD" "TARGET_INT_SIMD"
"uqsub<qaddsub_suf>%?\\t%0, %1, %2" "uqsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]) (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")])
(define_insn "sssub<mode>3" (define_insn "sssub<mode>3"
[(set (match_operand:QADDSUB 0 "s_register_operand" "=r") [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
...@@ -89,7 +96,8 @@ ...@@ -89,7 +96,8 @@
"TARGET_INT_SIMD" "TARGET_INT_SIMD"
"qsub<qaddsub_suf>%?\\t%0, %1, %2" "qsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]) (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_reg")])
;; Fractional multiplies. ;; Fractional multiplies.
...@@ -246,6 +254,7 @@ ...@@ -246,6 +254,7 @@
return ""; return "";
} }
[(set_attr "conds" "clob") [(set_attr "conds" "clob")
(set_attr "type" "multiple")
(set (attr "length") (set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes") (if_then_else (eq_attr "is_thumb" "yes")
(if_then_else (match_test "arm_restrict_it") (if_then_else (match_test "arm_restrict_it")
...@@ -305,6 +314,7 @@ ...@@ -305,6 +314,7 @@
return ""; return "";
} }
[(set_attr "conds" "clob") [(set_attr "conds" "clob")
(set_attr "type" "multiple")
(set (attr "length") (set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes") (if_then_else (eq_attr "is_thumb" "yes")
(if_then_else (match_test "arm_restrict_it") (if_then_else (match_test "arm_restrict_it")
...@@ -414,5 +424,6 @@ ...@@ -414,5 +424,6 @@
"TARGET_INT_SIMD" "TARGET_INT_SIMD"
"usat%?\\t%0, #16, %1" "usat%?\\t%0, #16, %1"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")] (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_imm")]
) )
gcc/config/arm/arm1020e.md
...@@ -71,7 +71,8 @@ ...@@ -71,7 +71,8 @@
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg")) mov_imm,mov_reg,mvn_imm,mvn_reg,\
multiple,no_insn"))
"1020a_e,1020a_m,1020a_w") "1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-constant operand ;; ALU operations with a shift-by-constant operand
......
gcc/config/arm/arm1026ejs.md
...@@ -71,7 +71,8 @@ ...@@ -71,7 +71,8 @@
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg")) mov_imm,mov_reg,mvn_imm,mvn_reg,\
multiple,no_insn"))
"a_e,a_m,a_w") "a_e,a_m,a_w")
;; ALU operations with a shift-by-constant operand ;; ALU operations with a shift-by-constant operand
......
gcc/config/arm/arm1136jfs.md
...@@ -80,7 +80,8 @@ ...@@ -80,7 +80,8 @@
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg")) mov_imm,mov_reg,mvn_imm,mvn_reg,\
multiple,no_insn"))
"e_1,e_2,e_3,e_wb") "e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-constant operand ;; ALU operations with a shift-by-constant operand
......
gcc/config/arm/arm926ejs.md
...@@ -66,7 +66,8 @@ ...@@ -66,7 +66,8 @@
logic_shift_imm,logics_shift_imm,\ logic_shift_imm,logics_shift_imm,\
shift_imm,shift_reg,extend,\ shift_imm,shift_reg,extend,\
mov_imm,mov_reg,mov_shift,\ mov_imm,mov_reg,mov_shift,\
mvn_imm,mvn_reg,mvn_shift")) mvn_imm,mvn_reg,mvn_shift,\
multiple,no_insn"))
"e,m,w") "e,m,w")
;; ALU operations with a shift-by-register operand ;; ALU operations with a shift-by-register operand
......
gcc/config/arm/cortex-a15.md
...@@ -67,7 +67,8 @@ ...@@ -67,7 +67,8 @@
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,\ mov_imm,mov_reg,\
mvn_imm,mvn_reg")) mvn_imm,mvn_reg,\
multiple,no_insn"))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)") "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift ;; ALU ops with immediate shift
......
gcc/config/arm/cortex-a5.md
...@@ -63,7 +63,8 @@ ...@@ -63,7 +63,8 @@
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg")) mov_imm,mov_reg,mvn_imm,mvn_reg,\
multiple,no_insn"))
"cortex_a5_ex1") "cortex_a5_ex1")
(define_insn_reservation "cortex_a5_alu_shift" 2 (define_insn_reservation "cortex_a5_alu_shift" 2
......
gcc/config/arm/cortex-a53.md
...@@ -72,7 +72,8 @@ ...@@ -72,7 +72,8 @@
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,csel,rev,\ adr,bfm,csel,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg")) mov_imm,mov_reg,mvn_imm,mvn_reg,\
multiple,no_insn"))
"cortex_a53_slot_any") "cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift" 2 (define_insn_reservation "cortex_a53_alu_shift" 2
...@@ -81,7 +82,7 @@ ...@@ -81,7 +82,7 @@
logic_shift_imm,logics_shift_imm,\ logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\ alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\ logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\ extend,mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg")) mvn_shift,mvn_shift_reg"))
"cortex_a53_slot_any") "cortex_a53_slot_any")
......
gcc/config/arm/cortex-a7.md
...@@ -109,7 +109,8 @@ ...@@ -109,7 +109,8 @@
alu_shift_reg,alus_shift_reg,\ alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\ logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\ mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg")) mvn_shift,mvn_shift_reg,\
multiple,no_insn"))
"cortex_a7_ex1") "cortex_a7_ex1")
;; Forwarding path for unshifted operands. ;; Forwarding path for unshifted operands.
......
gcc/config/arm/cortex-a8.md
...@@ -89,7 +89,8 @@ ...@@ -89,7 +89,8 @@
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,\ adr,bfm,clz,rbit,rev,\
shift_imm,shift_reg")) shift_imm,shift_reg,\
multiple,no_insn"))
"cortex_a8_default") "cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2 (define_insn_reservation "cortex_a8_alu_shift" 2
......
gcc/config/arm/cortex-a9.md
...@@ -86,7 +86,8 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") ...@@ -86,7 +86,8 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\
mov_shift_reg,mov_shift")) mov_shift_reg,mov_shift,\
multiple,no_insn"))
"cortex_a9_p0_default|cortex_a9_p1_default") "cortex_a9_p0_default|cortex_a9_p1_default")
;; An instruction using the shifter will go down E1. ;; An instruction using the shifter will go down E1.
......
gcc/config/arm/cortex-m4.md
...@@ -41,7 +41,8 @@ ...@@ -41,7 +41,8 @@
alu_shift_reg,alus_shift_reg,\ alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\ logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\ mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg") mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
multiple,no_insn")
(ior (eq_attr "mul32" "yes") (ior (eq_attr "mul32" "yes")
(eq_attr "mul64" "yes")))) (eq_attr "mul64" "yes"))))
"cortex_m4_ex") "cortex_m4_ex")
......
gcc/config/arm/cortex-r4.md
...@@ -101,7 +101,8 @@ ...@@ -101,7 +101,8 @@
(and (eq_attr "tune_cortexr4" "yes") (and (eq_attr "tune_cortexr4" "yes")
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\ logic_shift_reg,logics_shift_reg,\
mov_shift_reg,mvn_shift_reg")) mov_shift_reg,mvn_shift_reg,\
multiple,no_insn"))
"cortex_r4_alu_shift_reg") "cortex_r4_alu_shift_reg")
;; An ALU instruction followed by an ALU instruction with no early dep. ;; An ALU instruction followed by an ALU instruction with no early dep.
......
gcc/config/arm/fa526.md
...@@ -67,7 +67,8 @@ ...@@ -67,7 +67,8 @@
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg")) mov_imm,mov_reg,mvn_imm,mvn_reg,\
multiple,no_insn"))
"fa526_core") "fa526_core")
(define_insn_reservation "526_alu_shift_op" 2 (define_insn_reservation "526_alu_shift_op" 2
......
gcc/config/arm/fa606te.md
...@@ -72,7 +72,8 @@ ...@@ -72,7 +72,8 @@
alu_shift_reg,alus_shift_reg,\ alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\ logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\ mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")) mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
multiple,no_insn"))
"fa606te_core") "fa606te_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
gcc/config/arm/fa626te.md
...@@ -73,7 +73,8 @@ ...@@ -73,7 +73,8 @@
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg,\ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg")) mov_imm,mov_reg,mvn_imm,mvn_reg,\
multiple,no_insn"))
"fa626te_core") "fa626te_core")
(define_insn_reservation "626te_alu_shift_op" 2 (define_insn_reservation "626te_alu_shift_op" 2
......
gcc/config/arm/fa726te.md
...@@ -90,7 +90,8 @@ ...@@ -90,7 +90,8 @@
alu_reg,alus_reg,logic_reg,logics_reg,\ alu_reg,alus_reg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\ adr,bfm,rev,\
shift_imm,shift_reg")) shift_imm,shift_reg,\
multiple,no_insn"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;; ALU operations with a shift-by-register operand. ;; ALU operations with a shift-by-register operand.
......
gcc/config/arm/types.md
...@@ -105,10 +105,14 @@ ...@@ -105,10 +105,14 @@
; mov_shift_reg simple MOV instruction, shifted operand by a register. ; mov_shift_reg simple MOV instruction, shifted operand by a register.
; mul integer multiply. ; mul integer multiply.
; muls integer multiply, flag setting. ; muls integer multiply, flag setting.
; multiple more than one instruction, candidate for future
; splitting, or better modeling.
; mvn_imm inverting move instruction, immediate. ; mvn_imm inverting move instruction, immediate.
; mvn_reg inverting move instruction, register. ; mvn_reg inverting move instruction, register.
; mvn_shift inverting move instruction, shifted operand by a constant. ; mvn_shift inverting move instruction, shifted operand by a constant.
; mvn_shift_reg inverting move instruction, shifted operand by a register. ; mvn_shift_reg inverting move instruction, shifted operand by a register.
; no_insn an insn which does not represent an instruction in the
; final output, thus having no impact on scheduling.
; rbit reverse bits. ; rbit reverse bits.
; rev reverse bytes. ; rev reverse bytes.
; sdiv signed division. ; sdiv signed division.
...@@ -150,6 +154,8 @@ ...@@ -150,6 +154,8 @@
; umlals unsigned multiply accumulate long, flag setting. ; umlals unsigned multiply accumulate long, flag setting.
; umull unsigned multiply long. ; umull unsigned multiply long.
; umulls unsigned multiply long, flag setting. ; umulls unsigned multiply long, flag setting.
; untyped insn without type information - default, and error,
; case.
; ;
; The classification below is for instructions used by the Wireless MMX ; The classification below is for instructions used by the Wireless MMX
; Technology. Each attribute value is used to classify an instruction of the ; Technology. Each attribute value is used to classify an instruction of the
...@@ -301,6 +307,7 @@ ...@@ -301,6 +307,7 @@
branch,\ branch,\
call,\ call,\
clz,\ clz,\
no_insn,\
csel,\ csel,\
extend,\ extend,\
f_cvt,\ f_cvt,\
...@@ -360,10 +367,12 @@ ...@@ -360,10 +367,12 @@
mov_shift_reg,\ mov_shift_reg,\
mul,\ mul,\
muls,\ muls,\
multiple,\
mvn_imm,\ mvn_imm,\
mvn_reg,\ mvn_reg,\
mvn_shift,\ mvn_shift,\
mvn_shift_reg,\ mvn_shift_reg,\
nop,\
rbit,\ rbit,\
rev,\ rev,\
sdiv,\ sdiv,\
...@@ -403,6 +412,7 @@ ...@@ -403,6 +412,7 @@
umlals,\ umlals,\
umull,\ umull,\
umulls,\ umulls,\
untyped,\
wmmx_tandc,\ wmmx_tandc,\
wmmx_tbcst,\ wmmx_tbcst,\
wmmx_textrc,\ wmmx_textrc,\
...@@ -524,7 +534,7 @@ ...@@ -524,7 +534,7 @@
neon_vst2_4_regs_vst3_vst4,\ neon_vst2_4_regs_vst3_vst4,\
neon_vst3_vst4_lane,\ neon_vst3_vst4_lane,\
neon_vst3_vst4" neon_vst3_vst4"
(const_string "alu_imm")) (const_string "untyped"))
; Is this an (integer side) multiply with a 32-bit (or smaller) result? ; Is this an (integer side) multiply with a 32-bit (or smaller) result?
(define_attr "mul32" "no,yes" (define_attr "mul32" "no,yes"
......
gcc/config/arm/vfp.md
...@@ -144,7 +144,7 @@ ...@@ -144,7 +144,7 @@
gcc_unreachable (); gcc_unreachable ();
} }
" "
[(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored") [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
(set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8) (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
(eq_attr "alternative" "2") (const_int 12) (eq_attr "alternative" "2") (const_int 12)
(eq_attr "alternative" "3") (const_int 16) (eq_attr "alternative" "3") (const_int 16)
...@@ -192,7 +192,7 @@ ...@@ -192,7 +192,7 @@
gcc_unreachable (); gcc_unreachable ();
} }
" "
[(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored") [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8) (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
(eq_attr "alternative" "2") (const_int 12) (eq_attr "alternative" "2") (const_int 12)
(eq_attr "alternative" "3") (const_int 16) (eq_attr "alternative" "3") (const_int 16)
...@@ -261,7 +261,7 @@ ...@@ -261,7 +261,7 @@
" "
[(set_attr "conds" "unconditional") [(set_attr "conds" "unconditional")
(set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\ (set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\
load1,store1,fcpys,*,f_mcr,f_mrc,*") load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple")
(set_attr "length" "4,4,4,4,4,4,4,4,8")] (set_attr "length" "4,4,4,4,4,4,4,4,8")]
) )
...@@ -311,7 +311,7 @@ ...@@ -311,7 +311,7 @@
} }
" "
[(set_attr "conds" "unconditional") [(set_attr "conds" "unconditional")
(set_attr "type" "load1,store1,fcpys,*,f_mcr,f_mrc,*") (set_attr "type" "load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple")
(set_attr "length" "4,4,4,4,4,4,8")] (set_attr "length" "4,4,4,4,4,4,8")]
) )
...@@ -429,7 +429,7 @@ ...@@ -429,7 +429,7 @@
} }
" "
[(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\ [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
load2,store2,ffarithd,*") load2,store2,ffarithd,multiple")
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8) (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7") (eq_attr "alternative" "7")
(if_then_else (if_then_else
...@@ -474,7 +474,7 @@ ...@@ -474,7 +474,7 @@
} }
" "
[(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\ [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
f_stored,load2,store2,ffarithd,*") f_stored,load2,store2,ffarithd,multiple")
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8) (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7") (eq_attr "alternative" "7")
(if_then_else (if_then_else
...@@ -578,7 +578,7 @@ ...@@ -578,7 +578,7 @@
ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
[(set_attr "conds" "use") [(set_attr "conds" "use")
(set_attr "length" "6,6,10,6,6,10,6,6,10") (set_attr "length" "6,6,10,6,6,10,6,6,10")
(set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")] (set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcrr,f_mrrc,f_mrrc,f_mrrc")]
) )
......
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