mov.md ("extendhipsi2"): New.

* config/m32c/mov.md ("extendhipsi2"): New.

* config/m32c/bitops.md (bset_qi): Add memsym_operand predicate.

* config/m32c/bitops.md (andhi3_24, iorhi3_24): Don't prefer HL class.
* config/m32c/mov.md (zero_extendqihi2): Likewise.

From-SVN: r142237

gcc/ChangeLog

+2008-11-26  DJ Delorie  <dj@redhat.com>
+
+	* config/m32c/mov.md ("extendhipsi2"): New.
+
+	* config/m32c/bitops.md (bset_qi): Add memsym_operand predicate.
+
+	* config/m32c/bitops.md (andhi3_24, iorhi3_24): Don't prefer HL class.
+	* config/m32c/mov.md (zero_extendqihi2): Likewise.
+
 2008-11-26  Adam Nemet  <anemet@caviumnetworks.com>
 
 	* config/mips/mips.md (clear_hazard): Rename to

gcc/config/m32c/bitops.md

@@ -43,7 +43,7 @@
   [(set (match_operand:QI 0 "memsym_operand" "+Si")
 	(ior:QI (subreg:QI (ashift:HI (const_int 1)
 				      (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
-		(match_operand:QI 2 "" "0")))]
+		(match_operand:QI 2 "memsym_operand" "0")))]
   "TARGET_A16"
   "bset\t%0[%1]"
   [(set_attr "flags" "n")]
@@ -190,7 +190,7 @@
   )
 
 (define_insn "andhi3_24"
-  [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,??Rmm,RhiSd,??Rmm")
+  [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,??Rmm,RhiSd,??Rmm")
 	(and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
 		(match_operand:HI 2 "mrai_operand" "ImB,Imw,ImB,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
   "TARGET_A24"
@@ -223,7 +223,7 @@
   )
 
 (define_insn "iorhi3_24"
-  [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,RhiSd,??Rmm,??Rmm")
+  [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,RhiSd,??Rmm,??Rmm")
 	(ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
 		(match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
   "TARGET_A24"

gcc/config/m32c/mov.md

@@ -338,6 +338,16 @@
   [(set_attr "flags" "x")]
   )
 
+(define_insn "extendhipsi2"
+  [(set (match_operand:PSI 0 "register_operand" "=R03")
+	(sign_extend:PSI (match_operand:HI 1 "register_operand" "0")))]
+  ""
+  "*
+   if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
+   else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
+  [(set_attr "flags" "x")]
+  )
+
 (define_insn "extendpsisi2"
   [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
 	(sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
@@ -371,7 +381,7 @@
   )
 
 (define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=Rhl,RhiSd*Rmm")
+  [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=?Rhl,RhiSd*Rmm")
 	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
   ""
   "@