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Commit 588f75d0 by Stuart Hastings Committed by Stuart Hastings
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i386.md: Typos in MMX/SSE immediate shifts. 

2004-01-08  Stuart Hastings  <stuart@apple.com>

	* config/i386/i386.md: Typos in MMX/SSE immediate shifts.
	* testsuite/gcc.dg/20020523-2.c (bail_if_no_sse): Moved cpu-ID code...
	testsuite/gcc.dg/i386-cpuid.h (i386_cpuid): ...to here, to share with...
	* testsuite/gcc.dg/i386-sse-6.c: ...this new testcase.

From-SVN: r75566
parent 3b458e6f
Showing with 73 additions and 33 deletions
gcc/ChangeLog
2004-01-08 Stuart Hastings <stuart@apple.com>
* config/i386/i386.md: Typos in MMX/SSE immediate shifts.
2004-01-08 Jan Hubicka <jh@suse.cz>
* cgraphunit.c (cgraph_decide_inlining): Fix typo.
......
gcc/config/i386/i386.md
......@@ -22388,7 +22388,7 @@
(define_insn "ashrv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
(match_operand:TI 2 "nonmemory_operand" "xi")))]
(match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psraw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22397,7 +22397,7 @@
(define_insn "ashrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
(match_operand:TI 2 "nonmemory_operand" "xi")))]
(match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrad\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22406,7 +22406,7 @@
(define_insn "lshrv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
(match_operand:TI 2 "nonmemory_operand" "xi")))]
(match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrlw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22415,7 +22415,7 @@
(define_insn "lshrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
(match_operand:TI 2 "nonmemory_operand" "xi")))]
(match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrld\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22424,7 +22424,7 @@
(define_insn "lshrv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
(match_operand:TI 2 "nonmemory_operand" "xi")))]
(match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrlq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22433,7 +22433,7 @@
(define_insn "ashlv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
(match_operand:TI 2 "nonmemory_operand" "xi")))]
(match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psllw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22442,7 +22442,7 @@
(define_insn "ashlv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
(match_operand:TI 2 "nonmemory_operand" "xi")))]
(match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"pslld\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22451,7 +22451,7 @@
(define_insn "ashlv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
(match_operand:TI 2 "nonmemory_operand" "xi")))]
(match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psllq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22460,7 +22460,7 @@
(define_insn "ashrv8hi3_ti"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
(subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psraw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22469,7 +22469,7 @@
(define_insn "ashrv4si3_ti"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
(subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psrad\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22478,7 +22478,7 @@
(define_insn "lshrv8hi3_ti"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
(subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psrlw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22487,7 +22487,7 @@
(define_insn "lshrv4si3_ti"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
(subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psrld\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22496,7 +22496,7 @@
(define_insn "lshrv2di3_ti"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
(subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psrlq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22505,7 +22505,7 @@
(define_insn "ashlv8hi3_ti"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
(subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psllw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22514,7 +22514,7 @@
(define_insn "ashlv4si3_ti"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
(subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"pslld\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......@@ -22523,7 +22523,7 @@
(define_insn "ashlv2di3_ti"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
(subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
(subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
"TARGET_SSE2"
"psllq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
......
gcc/testsuite/ChangeLog
2004-01-08 Stuart Hastings <stuart@apple.com>
* testsuite/gcc.dg/20020523-2.c (bail_if_no_sse): Moved cpu-ID code...
testsuite/gcc.dg/i386-cpuid.h (i386_cpuid): ...to here, to share with...
* testsuite/gcc.dg/i386-sse-6.c: ...this new testcase.
2004-01-09 Alan Modra <amodra@bigpond.net.au>
* gcc.dg/array-quals-1.c: Accept .data.rel.ro.
......
gcc/testsuite/gcc.dg/20020523-2.c
......@@ -4,6 +4,7 @@
/* { dg-do run { target i386-*-* } } */
/* { dg-options "-march=pentium3 -msse -ffast-math -O2" } */
#include "i386-cpuid.h"
extern void abort (void);
extern void exit (int);
......@@ -27,24 +28,10 @@ typedef struct
void bail_if_no_sse (void)
{
int fl1, fl2;
/* See if we can use cpuid. */
__asm__ ("pushfl; pushfl; popl %0; movl %0,%1; xorl %2,%0;"
"pushl %0; popfl; pushfl; popl %0; popfl"
: "=&r" (fl1), "=&r" (fl2)
: "i" (0x00200000));
if (((fl1 ^ fl2) & 0x00200000) == 0)
exit (0);
/* See if cpuid gives capabilities. */
__asm__ ("cpuid" : "=a" (fl1) : "0" (0) : "ebx", "ecx", "edx", "cc");
if (fl1 == 0)
exit (0);
unsigned int edx;
/* See if capabilities include SSE (25th bit; 26 for SSE2). */
__asm__ ("cpuid" : "=a" (fl1), "=d" (fl2) : "0" (1) : "ebx", "ecx", "cc");
if ((fl2 & (1 << 25)) == 0)
edx = i386_cpuid();
if (!(edx & bit_SSE))
exit (0);
}
......
gcc/testsuite/gcc.dg/i386-cpuid.h 0 → 100644
/* Helper file for i386 platform. Runtime check for MMX/SSE/SSE2 support.
Used by 20020523-2.c and i386-sse-6.c, and possibly others. */
/* Plagarized from 20020523-2.c. */
#define bit_MMX (1 << 23)
#define bit_SSE (1 << 25)
#define bit_SSE2 (1 << 26)
#ifndef NOINLINE
#define NOINLINE __attribute__ ((noinline))
#endif
unsigned int i386_cpuid (void) NOINLINE;
unsigned int NOINLINE
i386_cpuid (void)
{
int fl1, fl2;
/* See if we can use cpuid. */
__asm__ ("pushfl; pushfl; popl %0; movl %0,%1; xorl %2,%0;"
"pushl %0; popfl; pushfl; popl %0; popfl"
: "=&r" (fl1), "=&r" (fl2)
: "i" (0x00200000));
if (((fl1 ^ fl2) & 0x00200000) == 0)
return (0);
/* Host supports cpuid. See if cpuid gives capabilities, try
CPUID(0). Preserve %ebx and %ecx; cpuid insn clobbers these, we
don't need their CPUID values here, and %ebx may be the PIC
register. */
__asm__ ("push %%ecx ; push %%ebx ; cpuid ; pop %%ebx ; pop %%ecx"
: "=a" (fl1) : "0" (0) : "edx", "cc");
if (fl1 == 0)
return (0);
/* Invoke CPUID(1), return %edx; caller can examine bits to
determine what's supported. */
__asm__ ("push %%ecx ; push %%ebx ; cpuid ; pop %%ebx ; pop %%ecx" : "=d" (fl2) : "a" (1) : "cc");
return fl2;
}
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