re PR rtl-optimization/59317 ([LRA,MIPS] ICE: in check_rtl, at lra.c (insn does…

re PR rtl-optimization/59317 ([LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints))

2013-12-05  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/59317
	* lra-constraints.c (in_class_p): Don't ignore insn with constant
	as a source.

2013-12-05  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/59317
	* testsuite/gcc.target/mips/pr59317.c: New.

From-SVN: r205718

gcc/ChangeLog

+2013-12-05  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR rtl-optimization/59317
+	* lra-constraints.c (in_class_p): Don't ignore insn with constant
+	as a source.
+
 2013-12-05  Martin Jambor  <mjambor@suse.cz>
 
 	PR ipa/58253

gcc/lra-constraints.c

@@ -271,9 +271,11 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
 	 where other reload pseudos are no longer allocatable.  */
       || (INSN_UID (curr_insn) >= new_insn_uid_start
 	  && curr_insn_set != NULL
-	  && (OBJECT_P (SET_SRC (curr_insn_set))
+	  && ((OBJECT_P (SET_SRC (curr_insn_set))
+	       && ! CONSTANT_P (SET_SRC (curr_insn_set)))
 	      || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
-		  && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
+		  && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
+		  && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
     /* When we don't know what class will be used finally for reload
        pseudos, we use ALL_REGS.  */
     return ((regno >= new_regno_start && rclass == ALL_REGS)

gcc/testsuite/ChangeLog

+2013-12-05  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR rtl-optimization/59317
+	* testsuite/gcc.target/mips/pr59317.c: New.
+
 2013-12-05  Marek Polacek  <polacek@redhat.com>
 
 	PR sanitizer/59333

gcc/testsuite/gcc.target/mips/pr59317.c

+/* { dg-do compile } */
+/* { dg-options "-mips16" } */
+extern void abort();
+
+int i_0, i_1, i_2, i_3, i_4, i_5, i_6, i_7, i_8, i_9;
+int j_0, j_1, j_2, j_3, j_4, j_5, j_6, j_7, j_8, j_9;
+
+int main()
+{
+  register int *x1 = &i_1; 
+  register int *x2 = &i_2; 
+  register int *x3 = &i_3; 
+  register int *x4 = &i_4; 
+  register int *x5 = &i_5; 
+  register int *x6 = &i_6;
+  register int *x7 = &i_7; 
+  register int *x8 = &i_8; 
+  register int *x9 = &i_9;
+  
+  register int *y0 = &j_0; 
+  register int *y1 = &j_1; 
+  register int *y2 = &i_2; 
+  register int *y3 = &j_3; 
+  register int *y4 = &j_4; 
+  register int *y5 = &j_5; 
+  register int *y6 = &j_6; 
+  register int *y7 = &j_7; 
+  register int *y8 = &j_8; 
+  register int *y9 = &j_9;
+
+  asm volatile ("" : "=r" (x2) : "0" (x2)); 
+  asm volatile ("" : "=r" (x3) : "0" (x3)); 
+  asm volatile ("" : "=r" (x4) : "0" (x4)); 
+  asm volatile ("" : "=r" (x5) : "0" (x5)); 
+  asm volatile ("" : "=r" (x6) : "0" (x6)); 
+  asm volatile ("" : "=r" (x7) : "0" (x7)); 
+  asm volatile ("" : "=r" (x8) : "0" (x8)); 
+  asm volatile ("" : "=r" (x9) : "0" (x9));
+
+  asm volatile ("" : "=r" (y0) : "0" (y0)); 
+  asm volatile ("" : "=r" (y1) : "0" (y1)); 
+  asm volatile ("" : "=r" (y2) : "0" (y2)); 
+  asm volatile ("" : "=r" (y3) : "0" (y3)); 
+  asm volatile ("" : "=r" (y4) : "0" (y4));
+  asm volatile ("" : "=r" (y5) : "0" (y5)); 
+  asm volatile ("" : "=r" (y6) : "0" (y6)); 
+  asm volatile ("" : "=r" (y7) : "0" (y7)); 
+  asm volatile ("" : "=r" (y8) : "0" (y8)); 
+  asm volatile ("" : "=r" (y9) : "0" (y9));
+
+  asm volatile ("" : "=r" (x1) : "0" (x1)); 
+  asm volatile ("" : "=r" (x2) : "0" (x2)); 
+  asm volatile ("" : "=r" (x3) : "0" (x3)); 
+  asm volatile ("" : "=r" (x4) : "0" (x4)); 
+  asm volatile ("" : "=r" (x5) : "0" (x5)); 
+  asm volatile ("" : "=r" (x6) : "0" (x6)); 
+  asm volatile ("" : "=r" (x7) : "0" (x7)); 
+  asm volatile ("" : "=r" (x8) : "0" (x8)); 
+  asm volatile ("" : "=r" (x9) : "0" (x9));
+
+  asm volatile ("" : "=r" (y0) : "0" (y0)); 
+  asm volatile ("" : "=r" (y1) : "0" (y1)); 
+  asm volatile ("" : "=r" (y2) : "0" (y2)); 
+  asm volatile ("" : "=r" (y3) : "0" (y3)); 
+  asm volatile ("" : "=r" (y4) : "0" (y4)); 
+  asm volatile ("" : "=r" (y5) : "0" (y5)); 
+  asm volatile ("" : "=r" (y6) : "0" (y6)); 
+  asm volatile ("" : "=r" (y7) : "0" (y7)); 
+  asm volatile ("" : "=r" (y8) : "0" (y8)); 
+  asm volatile ("" : "=r" (y9) : "0" (y9));
+
+  if (y0 != &j_0) abort (); 
+  if (y1 != &j_1) abort (); 
+  if (y2 != &j_2) abort (); 
+  if (y3 != &j_3) abort (); 
+  if (y4 != &j_4) abort (); 
+  if (y5 != &j_5) abort (); 
+  if (y6 != &j_6) abort (); 
+  if (y7 != &j_7) abort (); 
+  if (y8 != &j_8) abort (); 
+  if (y9 != &j_9) abort ();
+  return 0;
+}