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Commit 583ca921 by Steve Ellcey Committed by Steve Ellcey
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re PR target/37846 (Option -mno-fused-madd should be supported on IA-64) 

	PR target/37846
	* config/ia64/ia64.opt (mfused-madd): New.
	* config/ia64/ia64.h (TARGET_DEFAULT): Set MASK_FUSED_MADD.
	* config/ia64/hpux.h (TARGET_DEFAULT): Ditto.
	* config/ia64/ia64.md (maddsf4, msubsf4, nmaddsf4,
	madddf4, madddf4_trunc, msubdf4, msubdf4_trunc, nmadddf4,
	nmadddf4_truncsf, maddxf4, maddxf4_truncsf, maddxf4_truncdf,
	msubxf4, msubxf4_truncsf msubxf4_truncdf, nmaddxf4,
	nmaddxf4_truncsf, nmaddxf4_truncdf): Check TARGET_FUSED_MADD.
	* config/ia64/vect.md (addv2sf3, subv2sf3): Force fpma/fpms 
	instruction if !TARGET_FUSED_MADD.
	(fpma, fpms): Remove colon from name.

From-SVN: r147782
parent 150e3929
Showing with 51 additions and 22 deletions
gcc/ChangeLog
2009-05-21 Steve Ellcey <sje@cup.hp.com>
PR target/37846
* config/ia64/ia64.opt (mfused-madd): New.
* config/ia64/ia64.h (TARGET_DEFAULT): Set MASK_FUSED_MADD.
* config/ia64/hpux.h (TARGET_DEFAULT): Ditto.
* config/ia64/ia64.md (maddsf4, msubsf4, nmaddsf4,
madddf4, madddf4_trunc, msubdf4, msubdf4_trunc, nmadddf4,
nmadddf4_truncsf, maddxf4, maddxf4_truncsf, maddxf4_truncdf,
msubxf4, msubxf4_truncsf msubxf4_truncdf, nmaddxf4,
nmaddxf4_truncsf, nmaddxf4_truncdf): Check TARGET_FUSED_MADD.
* config/ia64/vect.md (addv2sf3, subv2sf3): Force fpma/fpms
instruction if !TARGET_FUSED_MADD.
(fpma, fpms): Remove colon from name.
2009-05-22 Richard Guenther <rguenther@suse.de>
* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Record
......
gcc/config/ia64/hpux.h
......@@ -106,7 +106,7 @@ do { \
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_DWARF2_ASM | MASK_BIG_ENDIAN | MASK_ILP32)
(MASK_DWARF2_ASM | MASK_BIG_ENDIAN | MASK_ILP32 | MASK_FUSED_MADD)
/* ??? Might not be needed anymore. */
#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) ((MODE) == TFmode)
......
gcc/config/ia64/ia64.h
......@@ -94,7 +94,7 @@ enum ia64_inline_type
/* Default target_flags if no switches are specified */
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_DWARF2_ASM)
#define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_FUSED_MADD)
#endif
#ifndef TARGET_CPU_DEFAULT
......
gcc/config/ia64/ia64.md
......@@ -3106,7 +3106,7 @@
(plus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"TARGET_FUSED_MADD"
"fma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3115,7 +3115,7 @@
(minus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"TARGET_FUSED_MADD"
"fms.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3132,7 +3132,7 @@
(minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
(mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
"TARGET_FUSED_MADD"
"fnma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3303,7 +3303,7 @@
(plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"TARGET_FUSED_MADD"
"fma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3313,7 +3313,7 @@
(plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
"TARGET_FUSED_MADD"
"fma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3322,7 +3322,7 @@
(minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
"TARGET_FUSED_MADD"
"fms.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3332,7 +3332,7 @@
(minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
"TARGET_FUSED_MADD"
"fms.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3358,7 +3358,7 @@
(minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
(mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
"TARGET_FUSED_MADD"
"fnma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3378,7 +3378,7 @@
(minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
(mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))]
""
"TARGET_FUSED_MADD"
"fnma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3599,7 +3599,7 @@
(plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
(match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
""
"TARGET_FUSED_MADD"
"fma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3609,7 +3609,7 @@
(plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
(match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
""
"TARGET_FUSED_MADD"
"fma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3619,7 +3619,7 @@
(plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
(match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
""
"TARGET_FUSED_MADD"
"fma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3660,7 +3660,7 @@
(minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
(match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
""
"TARGET_FUSED_MADD"
"fms %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3670,7 +3670,7 @@
(minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
(match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
""
"TARGET_FUSED_MADD"
"fms.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3680,7 +3680,7 @@
(minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
(match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
""
"TARGET_FUSED_MADD"
"fms.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3718,7 +3718,7 @@
(mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
)))]
""
"TARGET_FUSED_MADD"
"fnma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3729,7 +3729,7 @@
(mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
))))]
""
"TARGET_FUSED_MADD"
"fnma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......@@ -3740,7 +3740,7 @@
(mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
))))]
""
"TARGET_FUSED_MADD"
"fnma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
......
gcc/config/ia64/ia64.opt
......@@ -178,4 +178,8 @@ msel-sched-dont-check-control-spec
Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
Don't generate checks for control speculation in selective scheduling
mfused-madd
Target Report Mask(FUSED_MADD)
Enable fused multiply/add and multiply/subtract instructions
; This comment is to ensure we retain the blank line above.
gcc/config/ia64/vect.md
......@@ -915,6 +915,11 @@
{
rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
if (!TARGET_FUSED_MADD)
{
emit_insn (gen_fpma (operands[0], operands[1], operands[3], operands[2]));
DONE;
}
})
;; The split condition here could be combine_completed, if we had such.
......@@ -960,6 +965,11 @@
{
rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
if (!TARGET_FUSED_MADD)
{
emit_insn (gen_fpms (operands[0], operands[1], operands[3], operands[2]));
DONE;
}
})
;; The split condition here could be combine_completed, if we had such.
......@@ -1001,7 +1011,7 @@
"fpmpy %0 = %1, %2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*fpma"
(define_insn "fpma"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(plus:V2SF
(mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
......@@ -1011,7 +1021,7 @@
"fpma %0 = %1, %2, %3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*fpms"
(define_insn "fpms"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(minus:V2SF
(mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
......
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