re PR target/40741 (code size explosion for integer comparison)

2009-10-28  Paolo Bonzini  <bonzini@gnu.org>

	PR rtl-optimization/40741
	* config/arm/arm.c (thumb1_rtx_costs): IOR or XOR with
	a small constant is cheap.
	* config/arm/arm.md (andsi3, iorsi3): Try to place the result of
	force_reg on the LHS.
	(xorsi3): Likewise, and split the XOR if the constant is complex
	and not in Thumb mode.

2009-10-28  Paolo Bonzini  <bonzini@gnu.org>

	PR rtl-optimization/40741
	* gcc.target/arm/thumb-branch1.c: New.

From-SVN: r153650

gcc/ChangeLog

 2009-10-28  Paolo Bonzini  <bonzini@gnu.org>
 
+	PR rtl-optimization/40741
+	* config/arm/arm.c (thumb1_rtx_costs): IOR or XOR with
+	a small constant is cheap.
+	* config/arm/arm.md (andsi3, iorsi3): Try to place the result of
+	force_reg on the LHS.
+	(xorsi3): Likewise, and split the XOR if the constant is complex
+	and not in Thumb mode.
+
+2009-10-28  Paolo Bonzini  <bonzini@gnu.org>
+
 	* expmed.c (emit_store_flag): Check costs before
 	transforming to the opposite representation.
 

gcc/config/arm/arm.c

@@ -6215,7 +6215,7 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
       else if ((outer == PLUS || outer == COMPARE)
 	       && INTVAL (x) < 256 && INTVAL (x) > -256)
 	return 0;
-      else if (outer == AND
+      else if ((outer == IOR || outer == XOR || outer == AND)
 	       && INTVAL (x) < 256 && INTVAL (x) >= -256)
 	return COSTS_N_INSNS (1);
       else if (outer == ASHIFT || outer == ASHIFTRT

gcc/config/arm/arm.md

@@ -1914,7 +1914,16 @@
   else /* TARGET_THUMB1 */
     {
       if (GET_CODE (operands[2]) != CONST_INT)
-        operands[2] = force_reg (SImode, operands[2]);
+        {
+          rtx tmp = force_reg (SImode, operands[2]);
+	  if (rtx_equal_p (operands[0], operands[1]))
+	    operands[2] = tmp;
+	  else
+	    {
+              operands[2] = operands[1];
+              operands[1] = tmp;
+	    }
+        }
       else
         {
           int i;
@@ -2623,7 +2632,16 @@
           DONE;
 	}
       else /* TARGET_THUMB1 */
-	operands [2] = force_reg (SImode, operands [2]);
+        {
+          rtx tmp = force_reg (SImode, operands[2]);
+	  if (rtx_equal_p (operands[0], operands[1]))
+	    operands[2] = tmp;
+	  else
+	    {
+              operands[2] = operands[1];
+              operands[1] = tmp;
+	    }
+        }
     }
   "
 )
@@ -2731,12 +2749,29 @@
 (define_expand "xorsi3"
   [(set (match_operand:SI         0 "s_register_operand" "")
 	(xor:SI (match_operand:SI 1 "s_register_operand" "")
-		(match_operand:SI 2 "arm_rhs_operand"  "")))]
+		(match_operand:SI 2 "reg_or_int_operand" "")))]
   "TARGET_EITHER"
-  "if (TARGET_THUMB1)
-     if (GET_CODE (operands[2]) == CONST_INT)
-       operands[2] = force_reg (SImode, operands[2]);
-  "
+  "if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      if (TARGET_32BIT)
+        {
+          arm_split_constant (XOR, SImode, NULL_RTX,
+	                      INTVAL (operands[2]), operands[0], operands[1],
+			      optimize && can_create_pseudo_p ());
+          DONE;
+	}
+      else /* TARGET_THUMB1 */
+        {
+          rtx tmp = force_reg (SImode, operands[2]);
+	  if (rtx_equal_p (operands[0], operands[1]))
+	    operands[2] = tmp;
+	  else
+	    {
+              operands[2] = operands[1];
+              operands[1] = tmp;
+	    }
+        }
+    }"
 )
 
 (define_insn "*arm_xorsi3"

gcc/testsuite/ChangeLog

+2009-10-28  Paolo Bonzini  <bonzini@gnu.org>
+
+	PR rtl-optimization/40741
+	* gcc.target/arm/thumb-branch1.c: New.
+
 2009-10-27  Jason Merrill  <jason@redhat.com>
 
 	* g++.dg/cpp0x/lambda/lambda-conv.C: New.

gcc/testsuite/gcc.target/arm/thumb-branch1.c

+/* { dg-do compile } */
+/* { dg-options "-Os -mthumb -march=armv5te" } */
+
+int returnbool(int a, int b)
+{
+    if (a < b)
+        return 1;
+    return 0;
+}
+
+/* { dg-final { scan-assembler-not "eor" } } */