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lvzhengyang
riscv-gcc-1
Commits
579cef8f
Commit
579cef8f
authored
Apr 16, 2015
by
Uros Bizjak
Committed by
Uros Bizjak
Apr 16, 2015
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i386.c (print_reg): Rewrite function.
* config/i386/i386.c (print_reg): Rewrite function. From-SVN: r222145
parent
dba0dd68
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gcc/config/i386/i386.c
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gcc/ChangeLog
View file @
579cef8f
2015-04-16 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (print_reg): Rewrite function.
2015-04-16 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
2015-04-16 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/s390/s390.h (IRA_HARD_REGNO_ADD_COST_MULTIPLIER):
* config/s390/s390.h (IRA_HARD_REGNO_ADD_COST_MULTIPLIER):
...
...
gcc/config/i386/i386.c
View file @
579cef8f
...
@@ -15191,8 +15191,9 @@ void
...
@@ -15191,8 +15191,9 @@ void
print_reg
(
rtx
x
,
int
code
,
FILE
*
file
)
print_reg
(
rtx
x
,
int
code
,
FILE
*
file
)
{
{
const
char
*
reg
;
const
char
*
reg
;
int
msize
;
unsigned
int
regno
;
unsigned
int
regno
;
bool
duplicated
=
code
==
'd'
&&
TARGET_AVX
;
bool
duplicated
;
if
(
ASSEMBLER_DIALECT
==
ASM_ATT
)
if
(
ASSEMBLER_DIALECT
==
ASM_ATT
)
putc
(
'%'
,
file
);
putc
(
'%'
,
file
);
...
@@ -15204,82 +15205,49 @@ print_reg (rtx x, int code, FILE *file)
...
@@ -15204,82 +15205,49 @@ print_reg (rtx x, int code, FILE *file)
return
;
return
;
}
}
regno
=
true_regnum
(
x
);
if
(
code
==
'y'
&&
STACK_TOP_P
(
x
))
gcc_assert
(
regno
!=
ARG_POINTER_REGNUM
{
&&
regno
!=
FRAME_POINTER_REGNUM
fputs
(
"st(0)"
,
file
);
&&
regno
!=
FLAGS_REG
return
;
&&
regno
!=
FPSR_REG
}
&&
regno
!=
FPCR_REG
);
if
(
code
==
'w'
)
if
(
code
==
'w'
)
cod
e
=
2
;
msiz
e
=
2
;
else
if
(
code
==
'b'
)
else
if
(
code
==
'b'
)
cod
e
=
1
;
msiz
e
=
1
;
else
if
(
code
==
'k'
)
else
if
(
code
==
'k'
)
cod
e
=
4
;
msiz
e
=
4
;
else
if
(
code
==
'q'
)
else
if
(
code
==
'q'
)
code
=
8
;
msize
=
8
;
else
if
(
code
==
'y'
)
code
=
3
;
else
if
(
code
==
'h'
)
else
if
(
code
==
'h'
)
cod
e
=
0
;
msiz
e
=
0
;
else
if
(
code
==
'x'
)
else
if
(
code
==
'x'
)
cod
e
=
16
;
msiz
e
=
16
;
else
if
(
code
==
't'
)
else
if
(
code
==
't'
)
cod
e
=
32
;
msiz
e
=
32
;
else
if
(
code
==
'g'
)
else
if
(
code
==
'g'
)
cod
e
=
64
;
msiz
e
=
64
;
else
else
cod
e
=
GET_MODE_SIZE
(
GET_MODE
(
x
));
msiz
e
=
GET_MODE_SIZE
(
GET_MODE
(
x
));
/* Irritatingly, AMD extended registers use different naming convention
regno
=
true_regnum
(
x
);
from the normal registers: "r%d[bwd]" */
if
(
REX_INT_REGNO_P
(
regno
))
{
gcc_assert
(
TARGET_64BIT
);
putc
(
'r'
,
file
);
fprint_ul
(
file
,
regno
-
FIRST_REX_INT_REG
+
8
);
switch
(
code
)
{
case
0
:
error
(
"extended registers have no high halves"
);
break
;
case
1
:
putc
(
'b'
,
file
);
break
;
case
2
:
putc
(
'w'
,
file
);
break
;
case
4
:
putc
(
'd'
,
file
);
break
;
case
8
:
/* no suffix */
break
;
default
:
error
(
"unsupported operand size for extended register"
);
break
;
}
return
;
}
reg
=
NULL
;
gcc_assert
(
regno
!=
ARG_POINTER_REGNUM
switch
(
code
)
&&
regno
!=
FRAME_POINTER_REGNUM
&&
regno
!=
FLAGS_REG
&&
regno
!=
FPSR_REG
&&
regno
!=
FPCR_REG
);
duplicated
=
code
==
'd'
&&
TARGET_AVX
;
switch
(
msize
)
{
{
case
3
:
if
(
STACK_TOP_P
(
x
))
{
reg
=
"st(0)"
;
break
;
}
/* FALLTHRU */
case
8
:
case
8
:
case
4
:
case
4
:
case
12
:
if
(
LEGACY_INT_REGNO_P
(
regno
))
if
(
LEGACY_INT_REG_P
(
x
))
putc
(
msize
==
8
?
'r'
:
'e'
,
file
);
putc
(
code
==
8
&&
TARGET_64BIT
?
'r'
:
'e'
,
file
);
/* FALLTHRU */
case
16
:
case
16
:
case
12
:
case
2
:
case
2
:
normal
:
normal
:
reg
=
hi_reg_name
[
regno
];
reg
=
hi_reg_name
[
regno
];
...
@@ -15296,19 +15264,49 @@ print_reg (rtx x, int code, FILE *file)
...
@@ -15296,19 +15264,49 @@ print_reg (rtx x, int code, FILE *file)
break
;
break
;
case
32
:
case
32
:
case
64
:
case
64
:
if
(
SSE_REG
_P
(
x
))
if
(
SSE_REG
NO_P
(
regno
))
{
{
gcc_assert
(
!
duplicated
);
gcc_assert
(
!
duplicated
);
putc
(
cod
e
==
32
?
'y'
:
'z'
,
file
);
putc
(
msiz
e
==
32
?
'y'
:
'z'
,
file
);
fputs
(
hi_reg_name
[
regno
]
+
1
,
file
)
;
reg
=
hi_reg_name
[
regno
]
+
1
;
return
;
break
;
}
}
break
;
goto
normal
;
default
:
default
:
gcc_unreachable
();
gcc_unreachable
();
}
}
fputs
(
reg
,
file
);
fputs
(
reg
,
file
);
/* Irritatingly, AMD extended registers use
different naming convention: "r%d[bwd]" */
if
(
REX_INT_REGNO_P
(
regno
))
{
gcc_assert
(
TARGET_64BIT
);
switch
(
msize
)
{
case
0
:
error
(
"extended registers have no high halves"
);
break
;
case
1
:
putc
(
'b'
,
file
);
break
;
case
2
:
putc
(
'w'
,
file
);
break
;
case
4
:
putc
(
'd'
,
file
);
break
;
case
8
:
/* no suffix */
break
;
default
:
error
(
"unsupported operand size for extended register"
);
break
;
}
return
;
}
if
(
duplicated
)
if
(
duplicated
)
{
{
if
(
ASSEMBLER_DIALECT
==
ASM_ATT
)
if
(
ASSEMBLER_DIALECT
==
ASM_ATT
)
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