Commit 572070ef by Paul Brook Committed by Paul Brook

arm-cores.def: Add cortex-r5.

2011-06-01  Paul Brook  <paul@cpodesourcery.com>

	gcc/
	* config/arm/arm-cores.def: Add cortex-r5.  Add DIV flags to
	Cortex-A15.
	* config/arm/arm-tune.md: Regenerate.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm.c (FL_DIV): Rename...
	(FL_THUMB_DIV): ... to this.
	(FL_ARM_DIV): Define.
	(FL_FOR_ARCH7R, FL_FOR_ARCH7M): Use FL_THUMB_DIV.
	(arm_arch_hwdiv): Remove.
	(arm_arch_thumb_hwdiv, arm_arch_arm_hwdiv): New variables.
	(arm_issue_rate): Add cortexr5.
	* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set
	__ARM_ARCH_EXT_IDIV__.
	(TARGET_IDIV): Define.
	(arm_arch_hwdiv): Remove.
	(arm_arch_arm_hwdiv, arm_arch_thumb_hwdiv): New prototypes.
	* config/arm/arm.md (tune_cortexr4): Add cortexr5.
	(divsi3, udivsi3): New patterns.
	* config/arm/thumb2.md (divsi3, udivsi3): Remove.
	* doc/invoke.texi: Document ARM -mcpu=cortex-r5

From-SVN: r174526
parent 6f59ea25
2011-06-01 Paul Brook <paul@cpodesourcery.com>
* config/arm/arm-cores.def: Add cortex-r5. Add DIV flags to
Cortex-A15.
* config/arm/arm-tune.md: Regenerate.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.c (FL_DIV): Rename...
(FL_THUMB_DIV): ... to this.
(FL_ARM_DIV): Define.
(FL_FOR_ARCH7R, FL_FOR_ARCH7M): Use FL_THUMB_DIV.
(arm_arch_hwdiv): Remove.
(arm_arch_thumb_hwdiv, arm_arch_arm_hwdiv): New variables.
(arm_issue_rate): Add cortexr5.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set
__ARM_ARCH_EXT_IDIV__.
(TARGET_IDIV): Define.
(arm_arch_hwdiv): Remove.
(arm_arch_arm_hwdiv, arm_arch_thumb_hwdiv): New prototypes.
* config/arm/arm.md (tune_cortexr4): Add cortexr5.
(divsi3, udivsi3): New patterns.
* config/arm/thumb2.md (divsi3, udivsi3): Remove.
* doc/invoke.texi: Document ARM -mcpu=cortex-r5
2011-06-01 Martin Jambor <mjambor@suse.cz> 2011-06-01 Martin Jambor <mjambor@suse.cz>
* ipa-utils.c (ipa_dfs_info): New field scc_no. * ipa-utils.c (ipa_dfs_info): New field scc_no.
......
...@@ -127,9 +127,10 @@ ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, 9e) ...@@ -127,9 +127,10 @@ ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, 9e)
ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e) ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e)
ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e) ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e)
ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED, 9e) ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, 9e)
ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e)
ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e)
ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, 9e)
ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e) ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e)
ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e) ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e)
ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e) ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e)
......
...@@ -250,6 +250,9 @@ EnumValue ...@@ -250,6 +250,9 @@ EnumValue
Enum(processor_type) String(cortex-r4f) Value(cortexr4f) Enum(processor_type) String(cortex-r4f) Value(cortexr4f)
EnumValue EnumValue
Enum(processor_type) String(cortex-r5) Value(cortexr5)
EnumValue
Enum(processor_type) String(cortex-m4) Value(cortexm4) Enum(processor_type) String(cortex-m4) Value(cortexm4)
EnumValue EnumValue
......
;; -*- buffer-read-only: t -*- ;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from arm-cores.def ;; Generated automatically by gentune.sh from arm-cores.def
(define_attr "tune" (define_attr "tune"
"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0" "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
(const (symbol_ref "((enum attr_tune) arm_tune)"))) (const (symbol_ref "((enum attr_tune) arm_tune)")))
...@@ -662,12 +662,13 @@ static int thumb_call_reg_needed; ...@@ -662,12 +662,13 @@ static int thumb_call_reg_needed;
#define FL_THUMB2 (1 << 16) /* Thumb-2. */ #define FL_THUMB2 (1 << 16) /* Thumb-2. */
#define FL_NOTM (1 << 17) /* Instructions not present in the 'M' #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
profile. */ profile. */
#define FL_DIV (1 << 18) /* Hardware divide. */ #define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
#define FL_NEON (1 << 20) /* Neon instructions. */ #define FL_NEON (1 << 20) /* Neon instructions. */
#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
architecture. */ architecture. */
#define FL_ARCH7 (1 << 22) /* Architecture 7. */ #define FL_ARCH7 (1 << 22) /* Architecture 7. */
#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
...@@ -694,8 +695,8 @@ static int thumb_call_reg_needed; ...@@ -694,8 +695,8 @@ static int thumb_call_reg_needed;
#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
/* The bits in this mask specify which /* The bits in this mask specify which
...@@ -781,7 +782,8 @@ int arm_cpp_interwork = 0; ...@@ -781,7 +782,8 @@ int arm_cpp_interwork = 0;
int arm_arch_thumb2; int arm_arch_thumb2;
/* Nonzero if chip supports integer division instruction. */ /* Nonzero if chip supports integer division instruction. */
int arm_arch_hwdiv; int arm_arch_arm_hwdiv;
int arm_arch_thumb_hwdiv;
/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference,
we must report the mode of the memory reference from we must report the mode of the memory reference from
...@@ -1449,7 +1451,8 @@ arm_option_override (void) ...@@ -1449,7 +1451,8 @@ arm_option_override (void)
arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
/* If we are not using the default (ARM mode) section anchor offset /* If we are not using the default (ARM mode) section anchor offset
...@@ -23019,6 +23022,7 @@ arm_issue_rate (void) ...@@ -23019,6 +23022,7 @@ arm_issue_rate (void)
{ {
case cortexr4: case cortexr4:
case cortexr4f: case cortexr4f:
case cortexr5:
case cortexa5: case cortexa5:
case cortexa8: case cortexa8:
case cortexa9: case cortexa9:
......
...@@ -101,6 +101,8 @@ extern char arm_arch_name[]; ...@@ -101,6 +101,8 @@ extern char arm_arch_name[];
builtin_define ("__ARM_PCS"); \ builtin_define ("__ARM_PCS"); \
builtin_define ("__ARM_EABI__"); \ builtin_define ("__ARM_EABI__"); \
} \ } \
if (TARGET_IDIV) \
builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
} while (0) } while (0)
#include "config/arm/arm-opts.h" #include "config/arm/arm-opts.h"
...@@ -290,6 +292,10 @@ extern void (*arm_lang_output_object_attributes_hook)(void); ...@@ -290,6 +292,10 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */ /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7) #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
/* Nonzero if integer division instructions supported. */
#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
|| (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
/* True iff the full BPABI is being used. If TARGET_BPABI is true, /* True iff the full BPABI is being used. If TARGET_BPABI is true,
then TARGET_AAPCS_BASED must be true -- but the converse does not then TARGET_AAPCS_BASED must be true -- but the converse does not
hold. TARGET_BPABI implies the use of the BPABI runtime library, hold. TARGET_BPABI implies the use of the BPABI runtime library,
...@@ -430,8 +436,11 @@ extern int arm_cpp_interwork; ...@@ -430,8 +436,11 @@ extern int arm_cpp_interwork;
/* Nonzero if chip supports Thumb 2. */ /* Nonzero if chip supports Thumb 2. */
extern int arm_arch_thumb2; extern int arm_arch_thumb2;
/* Nonzero if chip supports integer division instruction. */ /* Nonzero if chip supports integer division instruction in ARM mode. */
extern int arm_arch_hwdiv; extern int arm_arch_arm_hwdiv;
/* Nonzero if chip supports integer division instruction in Thumb mode. */
extern int arm_arch_thumb_hwdiv;
#ifndef TARGET_DEFAULT #ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APCS_FRAME) #define TARGET_DEFAULT (MASK_APCS_FRAME)
......
...@@ -496,7 +496,7 @@ ...@@ -496,7 +496,7 @@
(define_attr "tune_cortexr4" "yes,no" (define_attr "tune_cortexr4" "yes,no"
(const (if_then_else (const (if_then_else
(eq_attr "tune" "cortexr4,cortexr4f") (eq_attr "tune" "cortexr4,cortexr4f,cortexr5")
(const_string "yes") (const_string "yes")
(const_string "no")))) (const_string "no"))))
...@@ -3681,6 +3681,28 @@ ...@@ -3681,6 +3681,28 @@
(set_attr "predicable" "yes")] (set_attr "predicable" "yes")]
) )
;; Division instructions
(define_insn "divsi3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(div:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_IDIV"
"sdiv%?\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "insn" "sdiv")]
)
(define_insn "udivsi3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(udiv:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_IDIV"
"udiv%?\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "insn" "udiv")]
)
;; Unary arithmetic insns ;; Unary arithmetic insns
......
...@@ -779,26 +779,6 @@ ...@@ -779,26 +779,6 @@
(set_attr "length" "2")] (set_attr "length" "2")]
) )
(define_insn "divsi3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(div:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_THUMB2 && arm_arch_hwdiv"
"sdiv%?\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "insn" "sdiv")]
)
(define_insn "udivsi3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(udiv:SI (match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_THUMB2 && arm_arch_hwdiv"
"udiv%?\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "insn" "udiv")]
)
(define_insn "*thumb2_subsi_short" (define_insn "*thumb2_subsi_short"
[(set (match_operand:SI 0 "low_register_operand" "=l") [(set (match_operand:SI 0 "low_register_operand" "=l")
(minus:SI (match_operand:SI 1 "low_register_operand" "l") (minus:SI (match_operand:SI 1 "low_register_operand" "l")
......
...@@ -10241,7 +10241,8 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, ...@@ -10241,7 +10241,8 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250},
@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
@samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a15}, @samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a15},
@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
@samp{cortex-m4}, @samp{cortex-m3},
@samp{cortex-m1}, @samp{cortex-m1},
@samp{cortex-m0}, @samp{cortex-m0},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
......
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