Skip to content

R
riscv-gcc-1
Commit 5401050b by John David Anglin Committed by John David Anglin
Options

re PR target/20754 (ACATS cxg1005 fails at runtime on hppa-linux) 

	PR target/20754
	* pa.md: Create separate 32 and 64-bit move patterns for SI, DI, SF
	and DF modes.  Add alternatives to copy between general and floating
	point registers to the 32-bit patterns.
	* pa-64.h (SECONDARY_MEMORY_NEEDED_RTX): Delete undefine.
	* pa.h (SECONDARY_MEMORY_NEEDED_RTX): Delete define.
	(SECONDARY_MEMORY_NEEDED): Secondary memory is only needed when
	generating 64-bit code.
	* pa.c (output_move_double): Handle copies between general and
	floating registers.

From-SVN: r109557
parent 7d072037
Showing with 116 additions and 30 deletions
gcc/ChangeLog
2006-01-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR target/20754
* pa.md: Create separate 32 and 64-bit move patterns for SI, DI, SF
and DF modes. Add alternatives to copy between general and floating
point registers to the 32-bit patterns.
* pa-64.h (SECONDARY_MEMORY_NEEDED_RTX): Delete undefine.
* pa.h (SECONDARY_MEMORY_NEEDED_RTX): Delete define.
(SECONDARY_MEMORY_NEEDED): Secondary memory is only needed when
generating 64-bit code.
* pa.c (output_move_double): Handle copies between general and
floating registers.
2006-01-10 Stuart Hastings <stuart@apple.com> 2006-01-10 Stuart Hastings <stuart@apple.com>
* gcc/config/i386/i386.md (set_got): Update. * gcc/config/i386/i386.md (set_got): Update.
......
gcc/config/pa/pa-64.h
...@@ -70,10 +70,6 @@ Boston, MA 02110-1301, USA. */ ...@@ -70,10 +70,6 @@ Boston, MA 02110-1301, USA. */
relocs which appear in stabs. */ relocs which appear in stabs. */
#undef DBX_DEBUGGING_INFO #undef DBX_DEBUGGING_INFO
/* We want the compiler to select a suitable secondary memory location.
?!? This may not work reliably. Keep an eye out for problems. */
#undef SECONDARY_MEMORY_NEEDED_RTX
/* ?!? This needs to be made compile-time selectable. /* ?!? This needs to be made compile-time selectable.
The PA64 runtime model has arguments that grow to higher addresses The PA64 runtime model has arguments that grow to higher addresses
......
gcc/config/pa/pa.c
...@@ -2209,6 +2209,25 @@ output_move_double (rtx *operands) ...@@ -2209,6 +2209,25 @@ output_move_double (rtx *operands)
supposed to allow to happen. */ supposed to allow to happen. */
gcc_assert (optype0 == REGOP || optype1 == REGOP); gcc_assert (optype0 == REGOP || optype1 == REGOP);
/* Handle copies between general and floating registers. */
if (optype0 == REGOP && optype1 == REGOP
&& FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
{
if (FP_REG_P (operands[0]))
{
output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
return "{fldds|fldd} -16(%%sp),%0";
}
else
{
output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
return "{ldws|ldw} -12(%%sp),%R0";
}
}
/* Handle auto decrementing and incrementing loads and stores /* Handle auto decrementing and incrementing loads and stores
specifically, since the structure of the function doesn't work specifically, since the structure of the function doesn't work
for them without major modification. Do it better when we learn for them without major modification. Do it better when we learn
......
gcc/config/pa/pa.h
...@@ -531,14 +531,15 @@ extern struct rtx_def *hppa_pic_save_rtx (void); ...@@ -531,14 +531,15 @@ extern struct rtx_def *hppa_pic_save_rtx (void);
reg_classes_intersect_p ((CLASS), FP_REGS) reg_classes_intersect_p ((CLASS), FP_REGS)
/* On the PA it is not possible to directly move data between /* On the PA it is not possible to directly move data between
GENERAL_REGS and FP_REGS. */ GENERAL_REGS and FP_REGS. On the 32-bit port, we use the
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ location at SP-16. We don't expose this location in the RTL to
(MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \ avoid scheduling related problems. For example, the store and
|| MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1)) load could be separated by a call to a pure or const function
which has no frame and uses SP-16. */
/* Return the stack location to use for secondary memory needed reloads. */ #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ (TARGET_64BIT \
gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16))) && (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
|| MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1)))
/* Stack layout; function entry, exit and calling. */ /* Stack layout; function entry, exit and calling. */
......
gcc/config/pa/pa.md
...@@ -2307,12 +2307,41 @@ ...@@ -2307,12 +2307,41 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "move_dest_operand" [(set (match_operand:SI 0 "move_dest_operand"
"=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,r,f")
(match_operand:SI 1 "move_src_operand"
"A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,f,r"))]
"(register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))
&& !TARGET_SOFT_FLOAT
&& !TARGET_64BIT"
"@
ldw RT'%A1,%0
copy %1,%0
ldi %1,%0
ldil L'%1,%0
{zdepi|depwi,z} %Z1,%0
ldw%M1 %1,%0
stw%M0 %r1,%0
mtsar %r1
{mfctl|mfctl,w} %%sar,%0
fcpy,sgl %f1,%0
fldw%F1 %1,%0
fstw%F0 %1,%0
{fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
{stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
[(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,move,move")
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
(define_insn ""
[(set (match_operand:SI 0 "move_dest_operand"
"=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T") "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
(match_operand:SI 1 "move_src_operand" (match_operand:SI 1 "move_src_operand"
"A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))] "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
"(register_operand (operands[0], SImode) "(register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode)) || reg_or_0_operand (operands[1], SImode))
&& !TARGET_SOFT_FLOAT" && !TARGET_SOFT_FLOAT
&& TARGET_64BIT"
"@ "@
ldw RT'%A1,%0 ldw RT'%A1,%0
copy %1,%0 copy %1,%0
...@@ -3840,9 +3869,9 @@ ...@@ -3840,9 +3869,9 @@
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "move_dest_operand" [(set (match_operand:DF 0 "move_dest_operand"
"=f,*r,Q,?o,?Q,f,*r,*r") "=f,*r,Q,?o,?Q,f,*r,*r,r,f")
(match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand" (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
"fG,*rG,f,*r,*r,RQ,o,RQ"))] "fG,*rG,f,*r,*r,RQ,o,RQ,f,r"))]
"(register_operand (operands[0], DFmode) "(register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode)) || reg_or_0_operand (operands[1], DFmode))
&& !(GET_CODE (operands[1]) == CONST_DOUBLE && !(GET_CODE (operands[1]) == CONST_DOUBLE
...@@ -3851,13 +3880,15 @@ ...@@ -3851,13 +3880,15 @@
&& !TARGET_SOFT_FLOAT" && !TARGET_SOFT_FLOAT"
"* "*
{ {
if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]) if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
|| operands[1] == CONST0_RTX (DFmode)) || operands[1] == CONST0_RTX (DFmode))
&& !(REG_P (operands[0]) && REG_P (operands[1])
&& FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
return output_fp_move_double (operands); return output_fp_move_double (operands);
return output_move_double (operands); return output_move_double (operands);
}" }"
[(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load") [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,move,move")
(set_attr "length" "4,8,4,8,16,4,8,16")]) (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "indexed_memory_operand" "=R") [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
...@@ -4012,9 +4043,9 @@ ...@@ -4012,9 +4043,9 @@
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "move_dest_operand" [(set (match_operand:DF 0 "move_dest_operand"
"=r,?o,?Q,r,r") "=r,?o,?Q,r,r,r,f")
(match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand" (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
"rG,r,r,o,RQ"))] "rG,r,r,o,RQ,f,r"))]
"(register_operand (operands[0], DFmode) "(register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode)) || reg_or_0_operand (operands[1], DFmode))
&& !TARGET_64BIT && !TARGET_64BIT
...@@ -4023,8 +4054,8 @@ ...@@ -4023,8 +4054,8 @@
{ {
return output_move_double (operands); return output_move_double (operands);
}" }"
[(set_attr "type" "move,store,store,load,load") [(set_attr "type" "move,store,store,load,load,move,move")
(set_attr "length" "8,8,16,8,16")]) (set_attr "length" "8,8,16,8,16,12,12")])
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "move_dest_operand" [(set (match_operand:DF 0 "move_dest_operand"
...@@ -4154,22 +4185,25 @@ ...@@ -4154,22 +4185,25 @@
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "move_dest_operand" [(set (match_operand:DI 0 "move_dest_operand"
"=r,o,Q,r,r,r,*f,*f,T") "=r,o,Q,r,r,r,*f,*f,T,r,f")
(match_operand:DI 1 "general_operand" (match_operand:DI 1 "general_operand"
"rM,r,r,o*R,Q,i,*fM,RT,*f"))] "rM,r,r,o*R,Q,i,*fM,RT,*f,f,r"))]
"(register_operand (operands[0], DImode) "(register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode)) || reg_or_0_operand (operands[1], DImode))
&& !TARGET_64BIT && !TARGET_64BIT
&& !TARGET_SOFT_FLOAT" && !TARGET_SOFT_FLOAT"
"* "*
{ {
if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]) if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
|| (operands[1] == CONST0_RTX (DImode))) || operands[1] == CONST0_RTX (DFmode))
&& !(REG_P (operands[0]) && REG_P (operands[1])
&& FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
return output_fp_move_double (operands); return output_fp_move_double (operands);
return output_move_double (operands); return output_move_double (operands);
}" }"
[(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore") [(set_attr "type"
(set_attr "length" "8,8,16,8,16,16,4,4,4")]) "move,store,store,load,load,multi,fpalu,fpload,fpstore,move,move")
(set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "move_dest_operand" [(set (match_operand:DI 0 "move_dest_operand"
...@@ -4380,12 +4414,35 @@ ...@@ -4380,12 +4414,35 @@
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "move_dest_operand" [(set (match_operand:SF 0 "move_dest_operand"
"=f,!*r,f,*r,Q,Q,r,f")
(match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
"fG,!*rG,RQ,RQ,f,*rG,f,r"))]
"(register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))
&& !TARGET_SOFT_FLOAT
&& !TARGET_64BIT"
"@
fcpy,sgl %f1,%0
copy %r1,%0
fldw%F1 %1,%0
ldw%M1 %1,%0
fstw%F0 %1,%0
stw%M0 %r1,%0
{fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
{stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
[(set_attr "type" "fpalu,move,fpload,load,fpstore,store,move,move")
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4,4,4,4,4,4,8,8")])
(define_insn ""
[(set (match_operand:SF 0 "move_dest_operand"
"=f,!*r,f,*r,Q,Q") "=f,!*r,f,*r,Q,Q")
(match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand" (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
"fG,!*rG,RQ,RQ,f,*rG"))] "fG,!*rG,RQ,RQ,f,*rG"))]
"(register_operand (operands[0], SFmode) "(register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode)) || reg_or_0_operand (operands[1], SFmode))
&& !TARGET_SOFT_FLOAT" && !TARGET_SOFT_FLOAT
&& TARGET_64BIT"
"@ "@
fcpy,sgl %f1,%0 fcpy,sgl %f1,%0
copy %r1,%0 copy %r1,%0
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment