md.texi (Machine Constraints): Correct the meaning of constraints related to…

md.texi (Machine Constraints): Correct the meaning of constraints related to floating-point registers on SPARC.

	* doc/md.texi (Machine Constraints): Correct the meaning of
	constraints related to floating-point registers on SPARC.

From-SVN: r67481

gcc/ChangeLog

 2003-06-05  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* doc/md.texi (Machine Constraints): Correct the meaning of
+	constraints related to floating-point registers on SPARC.
+
+2003-06-05  Eric Botcazou  <ebotcazou@libertysurf.fr>
             Paolo Bonzini  <bonzini@gnu.org>
 
 	PR target/10663

gcc/doc/md.texi

@@ -2015,23 +2015,24 @@ Constants in the range @minus{}8 to 2
 @item SPARC---@file{sparc.h}
 @table @code
 @item f
-Floating-point register that can hold 32- or 64-bit values.
+Floating-point register on the SPARC-V8 architecture and
+lower floating-point register on the SPARC-V9 architecture.
 
 @item e
-Floating-point register that can hold 64- or 128-bit values.
+Floating-point register. It is equivalent to @samp{f} on the
+SPARC-V8 architecture and contains both lower and upper
+floating-point registers on the SPARC-V9 architecture.
 
 @item c
 Floating-point condition code register.
 
 @item d
-Floating-point register that can hold 32- or 64-bit values.
-It is only valid on the SPARC-V9 architecture when the Visual
-Instructions Set is available.
+Lower floating-point register. It is only valid on the SPARC-V9
+architecture when the Visual Instruction Set is available.
 
 @item b
-Floating-point register that can hold 64- or 128-bit values.
-It is only valid on the SPARC-V9 architecture when the Visual
-Instructions Set is available.
+Floating-point register. It is only valid on the SPARC-V9 architecture
+when the Visual Instruction Set is available.
 
 @item h
 64-bit global or out register for the SPARC-V8+ architecture.