target_attr_10.c: Add -mcpu=generic.

2017-08-06  Andrew Pinski  <apinski@cavium.com>

        * gcc.target/aarch64/target_attr_10.c: Add -mcpu=generic.
        * gcc.target/aarch64/target_attr_13.c: LIkewise.
        * gcc.target/aarch64/target_attr_15.c: LIkewise.
        * gcc.target/aarch64/target_attr_4.c: Likewise.
        * gcc.target/aarch64/target_attr_1.c: Add -march=armv8-a.
        * gcc.target/aarch64/target_attr_2.c: Likewise.
        * gcc.target/aarch64/target_attr_7.c: Likewise.
        * gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise.
        * gcc.target/aarch64/target_attr_crypto_ice_2.c: Likewise.
        * gcc.target/aarch64/target_attr_3.c: Add -mcpu=generic -march=armv8-a.

From-SVN: r250904

gcc/testsuite/ChangeLog

 2017-08-06  Andrew Pinski  <apinski@cavium.com>
 
+	* gcc.target/aarch64/target_attr_10.c: Add -mcpu=generic.
+	* gcc.target/aarch64/target_attr_13.c: LIkewise.
+	* gcc.target/aarch64/target_attr_15.c: LIkewise.
+	* gcc.target/aarch64/target_attr_4.c: Likewise.
+	* gcc.target/aarch64/target_attr_1.c: Add -march=armv8-a.
+	* gcc.target/aarch64/target_attr_2.c: Likewise.
+	* gcc.target/aarch64/target_attr_7.c: Likewise.
+	* gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise.
+	* gcc.target/aarch64/target_attr_crypto_ice_2.c: Likewise.
+	* gcc.target/aarch64/target_attr_3.c: Add -mcpu=generic -march=armv8-a.
+
+2017-08-06  Andrew Pinski  <apinski@cavium.com>
+
 	* gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: Pass
 	-march=armv8-a+nolse, skip if -mcpu= is passed.
 	* gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c: Likewise.

gcc/testsuite/gcc.target/aarch64/target_attr_1.c

 /* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx -dA" } */
+/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */
 
 /* Test that cpu attribute overrides the command-line -mcpu.  */
 

gcc/testsuite/gcc.target/aarch64/target_attr_10.c

 /* { dg-do compile } */
-/* { dg-options "-O2 -march=armv8-a+simd" } */
+/* { dg-options "-O2 -march=armv8-a+simd -mcpu=generic" } */
 
 /* Using a SIMD intrinsic from a function tagged with nosimd should fail
    due to inlining rules.  */

gcc/testsuite/gcc.target/aarch64/target_attr_13.c

 /* { dg-do assemble } */
-/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */
+/* { dg-options "-O2 -march=armv8-a+crc+crypto -mcpu=generic" } */
 
 #include "arm_acle.h"
 

gcc/testsuite/gcc.target/aarch64/target_attr_15.c

 /* { dg-do assemble } */
-/* { dg-options "-march=armv8-a+crypto -save-temps" } */
+/* { dg-options "-march=armv8-a+crypto -mcpu=generic -save-temps" } */
 
 /* Check that "+nothing" clears the ISA flags.  */
 

gcc/testsuite/gcc.target/aarch64/target_attr_2.c

 /* { dg-do assemble } */
-/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all" } */
+/* { dg-options "-O2 -mcpu=cortex-a57 -march=armv8-a -ftree-vectorize -fdump-tree-vect-all" } */
 
 /* The various ways to turn off simd availability should
    turn off vectorization.  */

gcc/testsuite/gcc.target/aarch64/target_attr_3.c

 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -save-temps" } */
+/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -march=armv8-a -mcpu=generic -save-temps" } */
 
 /* Check that the attribute overrides the command line option
    and the fix is applied once.  */

gcc/testsuite/gcc.target/aarch64/target_attr_4.c

 /* { dg-do assemble } */
-/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */
+/* { dg-options "-O2 -march=armv8-a+nocrc -mcpu=generic -save-temps" } */
 
 #include "arm_acle.h"
 

gcc/testsuite/gcc.target/aarch64/target_attr_7.c

 /* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx -dA" } */
+/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */
 
 /* Make sure that #pragma overrides command line option and
    target attribute overrides the pragma.  */

gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c

 /* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx+nofp" } */
+/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
 
 #include "arm_neon.h"
 

gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c

 /* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx+nofp" } */
+/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
 
 /* Make sure that we don't ICE when dealing with vector parameters
    in a simd-tagged function within a non-simd translation unit.  */