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Commit 52ff33d0 by Nathan Froyd Committed by Nathan Froyd
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rs6000.h (FIXED_SCRATCH): Use r0 as a scratch register on SPE targets. 

	* config/rs6000/rs6000.h (FIXED_SCRATCH): Use r0 as a scratch
	register on SPE targets.  Change documentation to reflect
	reality.
	* config/rs6000/rs6000.c (rs6000_conditional_register_usage):
	Change FIXED_SCRATCH to 14 and document why we're keeping r14
	out of the register allocation pool.
	(rs6000_reg_live_or_pic_offset_p): New function.
	(rs6000_emit_prologue): Move the actual saving of LR up to free
	r0 for holding r11.  Split saving of SPE 64-bit registers into
	its own case.  Ensure that offsets will always be in-range for
	'evstdd' by using r11 as a scratch register to point at the start
	of the SPE save area.  Save r11 if necessary, as it is the static
	chain register.
	(rs6000_emit_epilogue): Split restoring of SPE 64-bit registers
	into its own case.  Ensure that offsets will always be in-range
	for 'evldd' by using r11 as a scratch register to point at the
	start of the SPE save area.  Also adjust r11 when restoring
	the stack pointer to compensate for pre-loading r11.

From-SVN: r125340
parent b08f991d
Showing with 26 additions and 11 deletions
gcc/ChangeLog
2007-06-06 Nathan Froyd <froydnj@codesourcery.com>
* config/rs6000/rs6000.h (FIXED_SCRATCH): Use r0 as a scratch
register on SPE targets. Change documentation to reflect
reality.
* config/rs6000/rs6000.c (rs6000_conditional_register_usage):
Change FIXED_SCRATCH to 14 and document why we're keeping r14
out of the register allocation pool.
(rs6000_reg_live_or_pic_offset_p): New function.
(rs6000_emit_prologue): Move the actual saving of LR up to free
r0 for holding r11. Split saving of SPE 64-bit registers into
its own case. Ensure that offsets will always be in-range for
'evstdd' by using r11 as a scratch register to point at the start
of the SPE save area. Save r11 if necessary, as it is the static
chain register.
(rs6000_emit_epilogue): Split restoring of SPE 64-bit registers
into its own case. Ensure that offsets will always be in-range
for 'evldd' by using r11 as a scratch register to point at the
start of the SPE save area. Also adjust r11 when restoring
the stack pointer to compensate for pre-loading r11.
2007-06-05 Thomas Neumann <tneumann@users.sourceforge.net>
* cfg.c (init_flow): Use type safe memory macros.
......
gcc/config/rs6000/rs6000.h
......@@ -913,18 +913,12 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
/* A fixed register used at prologue and epilogue generation to fix
addressing modes. The SPE needs heavy addressing fixes at the last
minute, and it's best to save a register for it.
/* A fixed register used at epilogue generation to address SPE registers
with negative offsets. The 64-bit load/store instructions on the SPE
only take positive offsets (and small ones at that), so we need to
reserve a register for consing up negative offsets. */
AltiVec also needs fixes, but we've gotten around using r11, which
is actually wrong because when use_backchain_to_restore_sp is true,
we end up clobbering r11.
The AltiVec case needs to be fixed. Dunno if we should break ABI
compatibility and reserve a register for it as well.. */
#define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
#define FIXED_SCRATCH 0
/* Define this macro to change register usage conditional on target
flags. */
......
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