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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
52a661a6
Commit
52a661a6
authored
Apr 26, 2001
by
Jan Hubicka
Committed by
Jan Hubicka
Apr 26, 2001
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* (ix86_expand_fp_movcc): Re-enable SSE conditional move generation.
From-SVN: r41602
parent
8789b9fa
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2 deletions
+5
-2
gcc/ChangeLog
+4
-0
gcc/config/i386/i386.c
+1
-2
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gcc/ChangeLog
View file @
52a661a6
Thu
Apr
26
20
:
28
:
21
CEST
2001
Jan
Hubicka
<
jh
@suse
.
cz
>
*
(
ix86_expand_fp_movcc
)
:
Re
-
enable
SSE
conditional
move
generation
.
Thu
Apr
26
19
:
20
:
28
CEST
2001
Jan
Hubicka
<
jh
@suse
.
cz
>
Thu
Apr
26
19
:
20
:
28
CEST
2001
Jan
Hubicka
<
jh
@suse
.
cz
>
*
i386
.
md
(
abs
/
neg
splitter
)
:
Fix
calculation
of
sign
bit
for
TFmodes
*
i386
.
md
(
abs
/
neg
splitter
)
:
Fix
calculation
of
sign
bit
for
TFmodes
...
...
gcc/config/i386/i386.c
View file @
52a661a6
...
@@ -6613,8 +6613,7 @@ ix86_expand_fp_movcc (operands)
...
@@ -6613,8 +6613,7 @@ ix86_expand_fp_movcc (operands)
/* We may be called from the post-reload splitter. */
/* We may be called from the post-reload splitter. */
&&
(
!
REG_P
(
operands
[
0
])
&&
(
!
REG_P
(
operands
[
0
])
||
SSE_REG_P
(
operands
[
0
])
||
SSE_REG_P
(
operands
[
0
])
||
REGNO
(
operands
[
0
])
>=
FIRST_PSEUDO_REGISTER
)
||
REGNO
(
operands
[
0
])
>=
FIRST_PSEUDO_REGISTER
))
&&
0
)
{
{
rtx
op0
=
ix86_compare_op0
,
op1
=
ix86_compare_op1
;
rtx
op0
=
ix86_compare_op0
,
op1
=
ix86_compare_op1
;
code
=
GET_CODE
(
operands
[
1
]);
code
=
GET_CODE
(
operands
[
1
]);
...
...
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