arm.md (*addsi3_carryin_compare0_<optab>): New pattern.

	* config/arm/arm.md (*addsi3_carryin_compare0_<optab>): New pattern.
	(peephole2 for conditional move): Generate 16 bit instructions.

	* gcc.target/arm/pr46975.c: New testcase.

From-SVN: r174854

gcc/ChangeLog

+2011-06-09  Wei Guozhi  <carrot@google.com>
+
+	PR target/46975
+	* config/arm/arm.md (*addsi3_carryin_compare0_<optab>): New pattern.
+	(peephole2 for conditional move): Generate 16 bit instructions.
+
 2011-06-09  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/i386.md (*movdi_internal_rex64): Merge

gcc/config/arm/arm.md

@@ -985,6 +985,17 @@
 		      (const_string "alu_shift_reg")))]
 )
 
+(define_insn "*addsi3_carryin_clobercc_<optab>"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+	(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
+			  (match_operand:SI 2 "arm_rhs_operand" "rI"))
+		 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))
+   (clobber (reg:CC CC_REGNUM))]
+   "TARGET_32BIT"
+   "adc%.\\t%0, %1, %2"
+   [(set_attr "conds" "set")]
+)
+
 (define_expand "incscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
         (plus:SI (match_operator:SI 2 "arm_comparison_operator"
@@ -8873,14 +8884,19 @@
 	      (set (match_dup 0) (const_int 1)))
    (match_scratch:SI 3 "r")]
   "TARGET_32BIT"
-  [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
+  [(parallel
+    [(set (reg:CC CC_REGNUM)
+	  (compare:CC (match_dup 1) (match_dup 2)))
+     (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))])
    (parallel
     [(set (reg:CC CC_REGNUM)
 	  (compare:CC (const_int 0) (match_dup 3)))
      (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))])
-   (set (match_dup 0)
-	(plus:SI (plus:SI (match_dup 0) (match_dup 3))
-		 (geu:SI (reg:CC CC_REGNUM) (const_int 0))))])
+   (parallel
+    [(set (match_dup 0)
+	  (plus:SI (plus:SI (match_dup 0) (match_dup 3))
+		   (geu:SI (reg:CC CC_REGNUM) (const_int 0))))
+     (clobber (reg:CC CC_REGNUM))])])
 
 (define_insn "*cond_move"
   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")

gcc/testsuite/ChangeLog

+2011-06-09  Wei Guozhi  <carrot@google.com>
+
+	PR target/46975
+	* gcc.target/arm/pr46975.c: New testcase.
+
 2011-06-09  Nicola Pero  <nicola.pero@meta-innovation.com>
 
 	* objc-obj-c++-shared/objc-test-suite-next-encode-assist.h

gcc/testsuite/gcc.target/arm/pr46975.c

+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "subs" } } */
+/* { dg-final { scan-assembler "adcs" } } */
+
+int foo (int s)
+{
+      return s == 1;
+}