Skip to content

R
riscv-gcc-1
Commit 526b7aee by Saurabh Verma Committed by Joern Rennecke
Options

arc, arc: New directories. 

2013-10-01  Saurabh Verma  <saurabh.verma@codito.com>
            Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
            Joern Rennecke  <joern.rennecke@embecosm.com>
            Muhammad Khurram Riaz  <khurram.riaz@arc.com>
            Brendan Kehoe  <brendan@zen.org>
            Michael Eager  <eager@eagercon.com>
            Simon Cook  <simon.cook@embecosm.com>
            Jeremy Bennett  <jeremy.bennett@embecosm.com>

        * config/arc, common/config/arc: New directories.

Co-Authored-By: Brendan Kehoe <brendan@zen.org>
Co-Authored-By: Jeremy Bennett <jeremy.bennett@embecosm.com>
Co-Authored-By: Joern Rennecke <joern.rennecke@embecosm.com>
Co-Authored-By: Michael Eager <eager@eagercon.com>
Co-Authored-By: Muhammad Khurram Riaz <khurram.riaz@arc.com>
Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
Co-Authored-By: Simon Cook <simon.cook@embecosm.com>

From-SVN: r203072
parent 2a3e690a
Showing with 1178 additions and 0 deletions
gcc/ChangeLog
2013-10-01 Saurabh Verma <saurabh.verma@codito.com>
Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
Joern Rennecke <joern.rennecke@embecosm.com>
Muhammad Khurram Riaz <khurram.riaz@arc.com>
Brendan Kehoe <brendan@zen.org>
Michael Eager <eager@eagercon.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
* config/arc, common/config/arc: New directories.
2013-10-01 Joern Rennecke <joern.rennecke@embecosm.com>
Brendan Kehoe <brendan@zen.org>
Simon Cook <simon.cook@embecosm.com>
......
gcc/common/config/arc/arc-common.c 0 → 100644
/* Common hooks for Synopsys DesignWare ARC
Copyright (C) 1994, 1995, 1997, 1998, 2007-2013
Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "diagnostic-core.h"
#include "tm.h"
#include "common/common-target.h"
#include "opts.h"
#include "flags.h"
static void
arc_option_init_struct (struct gcc_options *opts)
{
opts->x_flag_no_common = 255; /* Mark as not user-initialized. */
/* Which cpu we're compiling for (A5, ARC600, ARC601, ARC700). */
arc_cpu = PROCESSOR_NONE;
}
/* Set default optimization options. */
/* The conditions are incomplete, so we rely on the evaluation order here,
which goes from first to last, i.e. the last match prevails. */
/* ??? But this trick only works for reject_negative options. Approximate
missing option combination. */
#define OPT_LEVELS_3_PLUS_SPEED_ONLY OPT_LEVELS_3_PLUS
static const struct default_options arc_option_optimization_table[] =
{
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_mRcq, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_mRcw, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_msize_level_, NULL, 1 },
{ OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 },
{ OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 },
{ OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_malign_call, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_mearly_cbranchsi, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_mbbit_peephole, NULL, 1 },
{ OPT_LEVELS_SIZE, OPT_mq_class, NULL, 1 },
{ OPT_LEVELS_SIZE, OPT_mcase_vector_pcrel, NULL, 1 },
{ OPT_LEVELS_SIZE, OPT_mcompact_casesi, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
/* Process options. */
static bool
arc_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
const struct cl_decoded_option *decoded,
location_t loc)
{
size_t code = decoded->opt_index;
int value = decoded->value;
switch (code)
{
static int mcpu_seen = PROCESSOR_NONE;
case OPT_mcpu_:
/* N.B., at this point arc_cpu has already been set to its new value by
our caller, so comparing arc_cpu with PROCESSOR_NONE is pointless. */
if (mcpu_seen != PROCESSOR_NONE && mcpu_seen != value)
warning_at (loc, 0, "multiple -mcpu= options specified.");
mcpu_seen = value;
switch (value)
{
case PROCESSOR_A5:
case PROCESSOR_ARC600:
case PROCESSOR_ARC700:
if (! (opts_set->x_target_flags & MASK_BARREL_SHIFTER) )
opts->x_target_flags |= MASK_BARREL_SHIFTER;
break;
case PROCESSOR_ARC601:
if (! (opts_set->x_target_flags & MASK_BARREL_SHIFTER) )
opts->x_target_flags &= ~MASK_BARREL_SHIFTER;
break;
default:
gcc_unreachable ();
}
}
return true;
}
#define TARGET_OPTION_INIT_STRUCT arc_option_init_struct
#define TARGET_OPTION_OPTIMIZATION_TABLE arc_option_optimization_table
#define TARGET_HANDLE_OPTION arc_handle_option
#define DEFAULT_NO_SDATA (TARGET_SDATA_DEFAULT ? 0 : MASK_NO_SDATA_SET)
/* We default to ARC700, which has the barrel shifter enabled. */
#define TARGET_DEFAULT_TARGET_FLAGS \
(MASK_BARREL_SHIFTER|MASK_VOLATILE_CACHE_SET|DEFAULT_NO_SDATA)
#include "common/common-target-def.h"
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
gcc/config/arc/arc-modes.def 0 → 100644
/* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu.
Copyright (C) 2002, 2007-2012 Free Software Foundation, Inc.
Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
on behalf of Synopsys Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Some insns set all condition code flags, some only set the ZNC flags, and
some only set the ZN flags. */
CC_MODE (CC_ZN);
CC_MODE (CC_Z);
CC_MODE (CC_C);
CC_MODE (CC_FP_GT);
CC_MODE (CC_FP_GE);
CC_MODE (CC_FP_ORD);
CC_MODE (CC_FP_UNEQ);
CC_MODE (CC_FPX);
/* Vector modes. */
VECTOR_MODES (INT, 4); /* V4QI V2HI */
VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
gcc/config/arc/arc-opts.h 0 → 100644
/* GCC option-handling definitions for the Synopsys DesignWare ARC architecture.
Copyright (C) 2007-2012 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
enum processor_type
{
PROCESSOR_NONE,
PROCESSOR_A5,
PROCESSOR_ARC600,
PROCESSOR_ARC601,
PROCESSOR_ARC700
};
gcc/config/arc/arc-protos.h 0 → 100644
/* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu.
Copyright (C) 2000, 2007-2013 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifdef RTX_CODE
extern enum machine_mode arc_select_cc_mode (enum rtx_code, rtx, rtx);
/* Define the function that build the compare insn for scc, bcc and mov*cc. */
extern struct rtx_def *gen_compare_reg (rtx, enum machine_mode);
/* Declarations for various fns used in the .md file. */
extern void arc_output_function_epilogue (FILE *, HOST_WIDE_INT, int);
extern const char *output_shift (rtx *);
extern bool compact_sda_memory_operand (rtx op,enum machine_mode mode);
extern bool arc_double_limm_p (rtx);
extern void arc_print_operand (FILE *, rtx, int);
extern void arc_print_operand_address (FILE *, rtx);
extern void arc_final_prescan_insn (rtx, rtx *, int);
extern void arc_set_default_type_attributes(tree type);
extern const char *arc_output_libcall (const char *);
extern bool prepare_extend_operands (rtx *operands, enum rtx_code code,
enum machine_mode omode);
extern int arc_output_addsi (rtx *operands, bool, bool);
extern int arc_output_commutative_cond_exec (rtx *operands, bool);
extern bool arc_expand_movmem (rtx *operands);
extern bool prepare_move_operands (rtx *operands, enum machine_mode mode);
extern void emit_shift (enum rtx_code, rtx, rtx, rtx);
#endif /* RTX_CODE */
#ifdef TREE_CODE
extern enum arc_function_type arc_compute_function_type (struct function *);
#endif /* TREE_CODE */
extern void arc_init (void);
extern unsigned int arc_compute_frame_size (int);
extern bool arc_ccfsm_branch_deleted_p (void);
extern void arc_ccfsm_record_branch_deleted (void);
extern rtx arc_legitimize_pic_address (rtx, rtx);
void arc_asm_output_aligned_decl_local (FILE *, tree, const char *,
unsigned HOST_WIDE_INT,
unsigned HOST_WIDE_INT,
unsigned HOST_WIDE_INT);
extern rtx arc_return_addr_rtx (int , rtx);
extern bool check_if_valid_regno_const (rtx *, int);
extern bool check_if_valid_sleep_operand (rtx *, int);
extern bool arc_legitimate_constant_p (enum machine_mode, rtx);
extern bool arc_legitimate_pc_offset_p (rtx);
extern bool arc_legitimate_pic_addr_p (rtx);
extern void emit_pic_move (rtx *, enum machine_mode);
extern bool arc_raw_symbolic_reference_mentioned_p (rtx, bool);
extern bool arc_legitimate_pic_operand_p (rtx);
extern bool arc_is_longcall_p (rtx);
extern bool arc_is_shortcall_p (rtx);
extern bool arc_profile_call (rtx callee);
extern bool valid_brcc_with_delay_p (rtx *);
extern bool small_data_pattern (rtx , enum machine_mode);
extern rtx arc_rewrite_small_data (rtx);
extern bool arc_ccfsm_cond_exec_p (void);
struct secondary_reload_info;
extern int arc_register_move_cost (enum machine_mode, enum reg_class,
enum reg_class);
extern rtx disi_highpart (rtx);
extern int arc_adjust_insn_length (rtx, int, bool);
extern int arc_corereg_hazard (rtx, rtx);
extern int arc_hazard (rtx, rtx);
extern int arc_write_ext_corereg (rtx);
extern rtx gen_acc1 (void);
extern rtx gen_acc2 (void);
extern rtx gen_mlo (void);
extern rtx gen_mhi (void);
extern bool arc_branch_size_unknown_p (void);
struct arc_ccfsm;
extern void arc_ccfsm_record_condition (rtx, bool, rtx, struct arc_ccfsm *);
extern void arc_expand_prologue (void);
extern void arc_expand_epilogue (int);
extern void arc_init_expanders (void);
extern int arc_check_millicode (rtx op, int offset, int load_p);
extern int arc_get_unalign (void);
extern void arc_clear_unalign (void);
extern void arc_toggle_unalign (void);
extern void split_addsi (rtx *);
extern void split_subsi (rtx *);
extern void arc_pad_return (void);
extern rtx arc_split_move (rtx *);
extern int arc_verify_short (rtx insn, int unalign, int);
extern const char *arc_short_long (rtx insn, const char *, const char *);
extern rtx arc_regno_use_in (unsigned int, rtx);
extern int arc_attr_type (rtx);
extern bool arc_scheduling_not_expected (void);
extern bool arc_sets_cc_p (rtx insn);
extern int arc_label_align (rtx label);
extern bool arc_need_delay (rtx insn);
extern bool arc_text_label (rtx);
extern int arc_decl_pretend_args (tree decl);
extern bool arc_short_comparison_p (rtx, int);
extern bool arc_epilogue_uses (int regno);
/* insn-attrtab.c doesn't include reload.h, which declares regno_clobbered_p. */
extern int regno_clobbered_p (unsigned int, rtx, enum machine_mode, int);
extern int arc_return_slot_offset (void);
extern bool arc_legitimize_reload_address (rtx *, enum machine_mode, int, int);
gcc/config/arc/arc-simd.h 0 → 100644
/* Synopsys DesignWare ARC SIMD include file.
Copyright (C) 2007-2012 Free Software Foundation, Inc.
Written by Saurabh Verma (saurabh.verma@celunite.com) on behalf os Synopsys
Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* As a special exception, if you include this header file into source
files compiled by GCC, this header file does not by itself cause
the resulting executable to be covered by the GNU General Public
License. This exception does not however invalidate any other
reasons why the executable file might be covered by the GNU General
Public License. */
#ifndef _ARC_SIMD_H
#define _ARC_SIMD_H 1
#ifndef __ARC_SIMD__
#error Use the "-msimd" flag to enable ARC SIMD support
#endif
/* I0-I7 registers. */
#define _IREG_I0 0
#define _IREG_I1 1
#define _IREG_I2 2
#define _IREG_I3 3
#define _IREG_I4 4
#define _IREG_I5 5
#define _IREG_I6 6
#define _IREG_I7 7
/* DMA configuration registers. */
#define _DMA_REG_DR0 0
#define _DMA_SDM_SRC_ADR_REG _DMA_REG_DR0
#define _DMA_SDM_DEST_ADR_REG _DMA_REG_DR0
#define _DMA_REG_DR1 1
#define _DMA_SDM_STRIDE_REG _DMA_REG_DR1
#define _DMA_REG_DR2 2
#define _DMA_BLK_REG _DMA_REG_DR2
#define _DMA_REG_DR3 3
#define _DMA_LOC_REG _DMA_REG_DR3
#define _DMA_REG_DR4 4
#define _DMA_SYS_SRC_ADR_REG _DMA_REG_DR4
#define _DMA_SYS_DEST_ADR_REG _DMA_REG_DR4
#define _DMA_REG_DR5 5
#define _DMA_SYS_STRIDE_REG _DMA_REG_DR5
#define _DMA_REG_DR6 6
#define _DMA_CFG_REG _DMA_REG_DR6
#define _DMA_REG_DR7 7
#define _DMA_FT_BASE_ADR_REG _DMA_REG_DR7
/* Predefined types used in vector instructions. */
typedef int __v4si __attribute__((vector_size(16)));
typedef short __v8hi __attribute__((vector_size(16)));
/* Synonyms */
#define _vaddaw __builtin_arc_vaddaw
#define _vaddw __builtin_arc_vaddw
#define _vavb __builtin_arc_vavb
#define _vavrb __builtin_arc_vavrb
#define _vdifaw __builtin_arc_vdifaw
#define _vdifw __builtin_arc_vdifw
#define _vmaxaw __builtin_arc_vmaxaw
#define _vmaxw __builtin_arc_vmaxw
#define _vminaw __builtin_arc_vminaw
#define _vminw __builtin_arc_vminw
#define _vmulaw __builtin_arc_vmulaw
#define _vmulfaw __builtin_arc_vmulfaw
#define _vmulfw __builtin_arc_vmulfw
#define _vmulw __builtin_arc_vmulw
#define _vsubaw __builtin_arc_vsubaw
#define _vsubw __builtin_arc_vsubw
#define _vsummw __builtin_arc_vsummw
#define _vand __builtin_arc_vand
#define _vandaw __builtin_arc_vandaw
#define _vbic __builtin_arc_vbic
#define _vbicaw __builtin_arc_vbicaw
#define _vor __builtin_arc_vor
#define _vxor __builtin_arc_vxor
#define _vxoraw __builtin_arc_vxoraw
#define _veqw __builtin_arc_veqw
#define _vlew __builtin_arc_vlew
#define _vltw __builtin_arc_vltw
#define _vnew __builtin_arc_vnew
#define _vmr1aw __builtin_arc_vmr1aw
#define _vmr1w __builtin_arc_vmr1w
#define _vmr2aw __builtin_arc_vmr2aw
#define _vmr2w __builtin_arc_vmr2w
#define _vmr3aw __builtin_arc_vmr3aw
#define _vmr3w __builtin_arc_vmr3w
#define _vmr4aw __builtin_arc_vmr4aw
#define _vmr4w __builtin_arc_vmr4w
#define _vmr5aw __builtin_arc_vmr5aw
#define _vmr5w __builtin_arc_vmr5w
#define _vmr6aw __builtin_arc_vmr6aw
#define _vmr6w __builtin_arc_vmr6w
#define _vmr7aw __builtin_arc_vmr7aw
#define _vmr7w __builtin_arc_vmr7w
#define _vmrb __builtin_arc_vmrb
#define _vh264f __builtin_arc_vh264f
#define _vh264ft __builtin_arc_vh264ft
#define _vh264fw __builtin_arc_vh264fw
#define _vvc1f __builtin_arc_vvc1f
#define _vvc1ft __builtin_arc_vvc1ft
#define _vbaddw __builtin_arc_vbaddw
#define _vbmaxw __builtin_arc_vbmaxw
#define _vbminw __builtin_arc_vbminw
#define _vbmulaw __builtin_arc_vbmulaw
#define _vbmulfw __builtin_arc_vbmulfw
#define _vbmulw __builtin_arc_vbmulw
#define _vbrsubw __builtin_arc_vbrsubw
#define _vbsubw __builtin_arc_vbsubw
#define _vasrw __builtin_arc_vasrw
#define _vsr8 __builtin_arc_vsr8
#define _vsr8aw __builtin_arc_vsr8aw
#define _vasrrwi __builtin_arc_vasrrwi
#define _vasrsrwi __builtin_arc_vasrsrwi
#define _vasrwi __builtin_arc_vasrwi
#define _vasrpwbi __builtin_arc_vasrpwbi
#define _vasrrpwbi __builtin_arc_vasrrpwbi
#define _vsr8awi __builtin_arc_vsr8awi
#define _vsr8i __builtin_arc_vsr8i
#define _vmvaw __builtin_arc_vmvaw
#define _vmvw __builtin_arc_vmvw
#define _vmvzw __builtin_arc_vmvzw
#define _vd6tapf __builtin_arc_vd6tapf
#define _vmovaw __builtin_arc_vmovaw
#define _vmovw __builtin_arc_vmovw
#define _vmovzw __builtin_arc_vmovzw
#define _vabsaw __builtin_arc_vabsaw
#define _vabsw __builtin_arc_vabsw
#define _vaddsuw __builtin_arc_vaddsuw
#define _vsignw __builtin_arc_vsignw
#define _vexch1 __builtin_arc_vexch1
#define _vexch2 __builtin_arc_vexch2
#define _vexch4 __builtin_arc_vexch4
#define _vupbaw __builtin_arc_vupbaw
#define _vupbw __builtin_arc_vupbw
#define _vupsbaw __builtin_arc_vupsbaw
#define _vupsbw __builtin_arc_vupsbw
#define _vdirun __builtin_arc_vdirun
#define _vdorun __builtin_arc_vdorun
#define _vdiwr __builtin_arc_vdiwr
#define _vdowr __builtin_arc_vdowr
#define _vrec __builtin_arc_vrec
#define _vrun __builtin_arc_vrun
#define _vrecrun __builtin_arc_vrecrun
#define _vendrec __builtin_arc_vendrec
#define _vld32wh __builtin_arc_vld32wh
#define _vld32wl __builtin_arc_vld32wl
#define _vld64 __builtin_arc_vld64
#define _vld32 __builtin_arc_vld32
#define _vld64w __builtin_arc_vld64w
#define _vld128 __builtin_arc_vld128
#define _vst128 __builtin_arc_vst128
#define _vst64 __builtin_arc_vst64
#define _vst16_n __builtin_arc_vst16_n
#define _vst32_n __builtin_arc_vst32_n
#define _vinti __builtin_arc_vinti
/* Additional synonyms to ease programming. */
#define _setup_dma_in_channel_reg _vdiwr
#define _setup_dma_out_channel_reg _vdowr
#endif /* _ARC_SIMD_H */
gcc/config/arc/arc.c 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/arc/arc.md 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/arc/arc600.md 0 → 100644
;; DFA scheduling description of the Synopsys DesignWare ARC600 cpu
;; for GNU C compiler
;; Copyright (C) 2007-2013 Free Software Foundation, Inc.
;; Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
;; on behalf of Synopsys Inc.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ARC600")
(define_cpu_unit "issue_600" "ARC600")
(define_cpu_unit "mul64_600" "ARC600")
; latency from flag-setting insns to branches is 3.
(define_insn_reservation "compare_600" 3
(and (eq_attr "tune" "arc600")
(eq_attr "type" "compare"))
"issue_600")
(define_insn_reservation "load_DI_600" 4
(and (eq_attr "tune" "arc600")
(eq_attr "type" "load")
(match_operand:DI 0 "" ""))
"issue_600")
(define_insn_reservation "load_600" 3
(and (eq_attr "tune" "arc600")
(eq_attr "type" "load")
(not (match_operand:DI 0 "" "")))
"issue_600")
(define_insn_reservation "mul_600_fast" 3
(and (eq_attr "tune" "arc600")
(match_test "arc_multcost < COSTS_N_INSNS (7)")
(eq_attr "type" "multi,umulti"))
"mul64_600*3")
(define_insn_reservation "mul_600_slow" 8
(and (eq_attr "tune" "arc600")
(match_test "arc_multcost >= COSTS_N_INSNS (7)")
(eq_attr "type" "multi,umulti"))
"mul64_600*8")
(define_insn_reservation "mul_mac_600" 3
(and (eq_attr "tune" "arc600")
(eq_attr "type" "mulmac_600"))
"nothing*3")
(define_bypass 1 "mul_mac_600" "mul_mac_600")
gcc/config/arc/arc700.md 0 → 100644
;; DFA scheduling description of the Synopsys DesignWare ARC700 cpu
;; for GNU C compiler
;; Comments and Support For ARC700 instructions added by
;; Saurabh Verma (saurabh.verma@codito.com)
;; Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
;; Factoring out and improvement of ARC700 Scheduling by
;; Joern Rennecke (joern.rennecke@embecosm.com)
;; Copyright (C) 2006-2012 Free Software Foundation, Inc.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ARC700")
;; aux to be added here
(define_cpu_unit "core, dmp, write_port, dmp_write_port, multiplier, issue, blockage, simd_unit" "ARC700")
(define_insn_reservation "core_insn_DI" 2
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "unary, move, cmove, binary")
(match_operand:DI 0 "" ""))
"issue+core, issue+core+write_port, write_port")
(define_insn_reservation "lr" 2
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "lr"))
"issue+blockage, blockage*2, write_port")
(define_insn_reservation "sr" 1
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "sr"))
"issue+dmp_write_port+blockage, blockage*9")
(define_insn_reservation "core_insn" 1
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "unary, move, binary"))
"issue+core, nothing, write_port")
(define_insn_reservation "cmove" 1
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "cmove"))
"issue+core, nothing, write_port")
(define_insn_reservation "cc_arith" 1
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "cc_arith"))
"issue+core, nothing, write_port")
(define_insn_reservation "two_cycle_core_insn" 2
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "two_cycle_core"))
"issue+core, nothing, write_port")
(define_insn_reservation "divaw_insn" 2
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "divaw"))
"issue+core, nothing, write_port")
(define_insn_reservation "shift_insn" 2
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "shift"))
"issue+core, nothing, write_port")
; Latency from flag setters to arithmetic with carry is 3.
(define_insn_reservation "compare_700" 3
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "compare"))
"issue+core, nothing, write_port")
; Assume here the branch is predicted correctly and has a delay slot insn
; or is properly unaligned.
(define_insn_reservation "branch_700" 1
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "compare"))
"issue+core, nothing, write_port")
; TODOs: is this correct ??
(define_insn_reservation "multi_DI" 10
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "multi")
(match_operand:DI 0 "" ""))
"issue+multiplier, multiplier*2,issue+multiplier, multiplier*2,
nothing,write_port,nothing*2, write_port")
(define_insn_reservation "umulti_DI" 9
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "umulti")
(match_operand:DI 0 "" ""))
"issue+multiplier, multiplier,issue+multiplier, multiplier*2,
write_port,nothing*3, write_port")
(define_insn_reservation "umulti_xmac" 5
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "umulti"))
"issue+multiplier, multiplier, nothing*3, write_port")
; latency of mpyu is lower than mpy / mpyh / mpyhu
(define_insn_reservation "umulti_std" 6
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "umulti"))
"issue+multiplier, multiplier*3, nothing*2, write_port")
;; arc700 xmac multiplier
(define_insn_reservation "multi_xmac" 5
(and (eq_attr "tune" "arc700_4_2_xmac")
(eq_attr "type" "multi"))
"issue+multiplier,multiplier,nothing*3,write_port")
; arc700 standard multiplier
(define_insn_reservation "multi_std" 7
(and (eq_attr "tune" "arc700_4_2_std")
(eq_attr "type" "multi"))
"issue+multiplier,multiplier*4,nothing*2,write_port")
;(define_insn_reservation "multi_SI" 7
; (eq_attr "type" "multi")
; "issue+multiplier, multiplier*2, nothing*4, write_port")
; There is no multiplier -> multiplier bypass except for the
; mac -> mac dependency on the accumulator.
; divaw -> divaw latency is 1 cycle
(define_bypass 1 "divaw_insn" "divaw_insn")
(define_bypass 1 "compare_700" "branch_700,core_insn,data_store,data_load")
; we could shedule the cmove immediately after the compare, but then
; the cmove would have higher latency... so just keep the cmove apart
; from the compare.
(define_bypass 2 "compare_700" "cmove")
; no functional unit runs when blockage is reserved
(exclusion_set "blockage" "core, multiplier")
(define_insn_reservation "data_load_DI" 4
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "load")
(match_operand:DI 0 "" ""))
"issue+dmp, issue+dmp, dmp_write_port, dmp_write_port")
(define_insn_reservation "data_load" 3
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "load")
(not (match_operand:DI 0 "" "")))
"issue+dmp, nothing, dmp_write_port")
(define_insn_reservation "data_store_DI" 2
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "store")
(match_operand:DI 0 "" ""))
"issue+dmp_write_port, issue+dmp_write_port")
(define_insn_reservation "data_store" 1
(and (eq_attr "tune_arc700" "true")
(eq_attr "type" "store")
(not (match_operand:DI 0 "" "")))
"issue+dmp_write_port")
gcc/config/arc/t-arc-newlib 0 → 100644
# GCC Makefile fragment for Synopsys DesignWare ARC with newlib.
# Copyright (C) 2007-2012 Free Software Foundation, Inc.
# This file is part of GCC.
# GCC is free software; you can redistribute it and/or modify it under the
# terms of the GNU General Public License as published by the Free Software
# Foundation; either version 3, or (at your option) any later version.
# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
# details.
# You should have received a copy of the GNU General Public License along
# with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# Selecting -mA5 uses the same functional multilib files/libraries
# as get used for -mARC600 aka -mA6.
MULTILIB_OPTIONS=mcpu=ARC600/mcpu=ARC601 mmul64/mmul32x16 mnorm
MULTILIB_DIRNAMES=arc600 arc601 mul64 mul32x16 norm
#
# Aliases:
MULTILIB_MATCHES = mcpu?ARC600=mcpu?arc600
MULTILIB_MATCHES += mcpu?ARC600=mARC600
MULTILIB_MATCHES += mcpu?ARC600=mA6
MULTILIB_MATCHES += mcpu?ARC600=mA5
MULTILIB_MATCHES += mcpu?ARC600=mno-mpy
MULTILIB_MATCHES += mcpu?ARC601=mcpu?arc601
MULTILIB_MATCHES += EL=mlittle-endian
MULTILIB_MATCHES += EB=mbig-endian
#
# These don't make sense for the ARC700 default target:
MULTILIB_EXCEPTIONS=mmul64* mmul32x16* mnorm*
# And neither of the -mmul* options make sense without -mnorm:
MULTILIB_EXCLUSIONS=mARC600/mmul64/!mnorm mcpu=ARC601/mmul64/!mnorm mARC600/mmul32x16/!mnorm
gcc/config/arc/t-arc-uClibc 0 → 100644
# GCC Makefile fragment for Synopsys DesignWare ARC with uClibc
# Copyright (C) 2007-2012 Free Software Foundation, Inc.
# This file is part of GCC.
# GCC is free software; you can redistribute it and/or modify it under the
# terms of the GNU General Public License as published by the Free Software
# Foundation; either version 3, or (at your option) any later version.
# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
# details.
# You should have received a copy of the GNU General Public License along
# with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
MULTILIB_EXTRA_OPTS = mno-sdata
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment