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riscv-gcc-1
Commit 52325f2c by Uros Bizjak
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i386.md (maxmin): New code iterator. 

	* config/i386/i386.md (maxmin): New code iterator.
	* config/i386/sse.md (<maxmin:code><mode>3): Macroize expander
	from <umaxmin:code><mode>3 and <smaxmin:code><mode>3 using maxmin
	code iterator.
	(*avx2_<maxmin:code><mode>3): Macroize isn from
	*avx2_<umaxmin:code><mode>3 and *avx2_<smaxmin:code><mode>3 using
	maxmin code iterator.
	(<smaxmin:code><VI124_128:mode>3): Merge with <smaxmin:code>v8hi3.
	(<umaxmin:code><VI124_128:mode>3): Merge with umaxv4si3 and
	<umaxmin:code>v16qi3.

From-SVN: r178981
parent 0b5f3ce7
Showing with 116 additions and 158 deletions
gcc/ChangeLog
2011-09-19 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (maxmin): New code iterator.
* config/i386/sse.md (<maxmin:code><mode>3): Macroize expander
from <umaxmin:code><mode>3 and <smaxmin:code><mode>3 using maxmin
code iterator.
(*avx2_<maxmin:code><mode>3): Macroize isn from
*avx2_<umaxmin:code><mode>3 and *avx2_<smaxmin:code><mode>3 using
maxmin code iterator.
(<smaxmin:code><VI124_128:mode>3): Merge with <smaxmin:code>v8hi3.
(<umaxmin:code><VI124_128:mode>3): Merge with umaxv4si3 and
<umaxmin:code>v16qi3.
2011-09-19 Alan Modra <amodra@gmail.com> 2011-09-19 Alan Modra <amodra@gmail.com>
Michael Meissner <meissner@linux.vnet.ibm.com> Michael Meissner <meissner@linux.vnet.ibm.com>
...@@ -36,7 +49,6 @@ ...@@ -36,7 +49,6 @@
2011-09-19 Paul Brook <paul@codesourcery.com> 2011-09-19 Paul Brook <paul@codesourcery.com>
gcc/
* config/arm/predicates.md (shift_amount_operand): Check constant * config/arm/predicates.md (shift_amount_operand): Check constant
shift count is in range. shift count is in range.
(const_shift_operand): Remove. (const_shift_operand): Remove.
...@@ -114,12 +126,10 @@ ...@@ -114,12 +126,10 @@
* config/i386/i386.c (ix86_build_const_vector): Handle V8SImode * config/i386/i386.c (ix86_build_const_vector): Handle V8SImode
and V4DImode. and V4DImode.
(ix86_build_signbit_mask): Likewise. (ix86_build_signbit_mask): Likewise.
(ix86_expand_int_vcond): Likewise. Handle V16HImode and (ix86_expand_int_vcond): Likewise. Handle V16HImode and V32QImode.
V32QImode.
(bdesc_args): Use CODE_FOR_{s,u}m{ax,in}v{32q,16h,8s}i3 (bdesc_args): Use CODE_FOR_{s,u}m{ax,in}v{32q,16h,8s}i3
instead of CODE_FOR_avx2_{s,u}m{ax,in}v{32q,16h,8s}i3. instead of CODE_FOR_avx2_{s,u}m{ax,in}v{32q,16h,8s}i3.
* config/i386/sse.md (avx2_<code><mode>3 umaxmin expand): Rename * config/i386/sse.md (avx2_<code><mode>3 umaxmin expand): Rename to...
to...
(<code><mode>3) ... this. (<code><mode>3) ... this.
(avx2_<code><mode>3 smaxmin expand): Rename to... (avx2_<code><mode>3 smaxmin expand): Rename to...
(<code><mode>3) ... this. (<code><mode>3) ... this.
...@@ -190,8 +200,7 @@ ...@@ -190,8 +200,7 @@
* Makefile.in (SYSROOT_CFLAGS_FOR_TARGET): Define from * Makefile.in (SYSROOT_CFLAGS_FOR_TARGET): Define from
@SYSROOT_CFLAGS_FOR_TARGET@. @SYSROOT_CFLAGS_FOR_TARGET@.
* configure.ac (SYSROOT_CFLAGS_FOR_TARGET): Set from * configure.ac (SYSROOT_CFLAGS_FOR_TARGET): Set from build-sysroot.
build-sysroot.
* configure: Regenerate. * configure: Regenerate.
(site.exp): Add definition of TEST_ALWAYS_FLAGS. (site.exp): Add definition of TEST_ALWAYS_FLAGS.
Remove setting of GCC_UNDER_TEST. Remove setting of GCC_UNDER_TEST.
gcc/config/i386/i386.md
...@@ -751,6 +751,9 @@ ...@@ -751,6 +751,9 @@
(define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%") (define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%")
(minus "") (ss_minus "") (us_minus "")]) (minus "") (ss_minus "") (us_minus "")])
;; Mapping of max and min
(define_code_iterator maxmin [smax smin umax umin])
;; Mapping of signed max and min ;; Mapping of signed max and min
(define_code_iterator smaxmin [smax smin]) (define_code_iterator smaxmin [smax smin])
......
gcc/config/i386/sse.md
...@@ -5831,9 +5831,10 @@ ...@@ -5831,9 +5831,10 @@
(set_attr "prefix" "orig,vex") (set_attr "prefix" "orig,vex")
(set_attr "mode" "<sseinsnmode>")]) (set_attr "mode" "<sseinsnmode>")])
(define_expand "<code><mode>3" (define_expand "<code><mode>3"
[(set (match_operand:VI124_256 0 "register_operand" "") [(set (match_operand:VI124_256 0 "register_operand" "")
(umaxmin:VI124_256 (maxmin:VI124_256
(match_operand:VI124_256 1 "nonimmediate_operand" "") (match_operand:VI124_256 1 "nonimmediate_operand" "")
(match_operand:VI124_256 2 "nonimmediate_operand" "")))] (match_operand:VI124_256 2 "nonimmediate_operand" "")))]
"TARGET_AVX2" "TARGET_AVX2"
...@@ -5841,7 +5842,7 @@ ...@@ -5841,7 +5842,7 @@
(define_insn "*avx2_<code><mode>3" (define_insn "*avx2_<code><mode>3"
[(set (match_operand:VI124_256 0 "register_operand" "=x") [(set (match_operand:VI124_256 0 "register_operand" "=x")
(umaxmin:VI124_256 (maxmin:VI124_256
(match_operand:VI124_256 1 "nonimmediate_operand" "%x") (match_operand:VI124_256 1 "nonimmediate_operand" "%x")
(match_operand:VI124_256 2 "nonimmediate_operand" "xm")))] (match_operand:VI124_256 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
...@@ -5852,24 +5853,74 @@ ...@@ -5852,24 +5853,74 @@
(set_attr "mode" "OI")]) (set_attr "mode" "OI")])
(define_expand "<code><mode>3" (define_expand "<code><mode>3"
[(set (match_operand:VI124_256 0 "register_operand" "") [(set (match_operand:VI8_AVX2 0 "register_operand" "")
(smaxmin:VI124_256 (maxmin:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "")
(match_operand:VI124_256 1 "nonimmediate_operand" "") (match_operand:VI8_AVX2 2 "register_operand" "")))]
(match_operand:VI124_256 2 "nonimmediate_operand" "")))] "TARGET_SSE4_2"
"TARGET_AVX2" {
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") enum rtx_code code;
rtx xops[6];
bool ok;
(define_insn "*avx2_<code><mode>3" xops[0] = operands[0];
[(set (match_operand:VI124_256 0 "register_operand" "=x")
(smaxmin:VI124_256 if (<CODE> == SMAX || <CODE> == UMAX)
(match_operand:VI124_256 1 "nonimmediate_operand" "%x") {
(match_operand:VI124_256 2 "nonimmediate_operand" "xm")))] xops[1] = operands[1];
"TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" xops[2] = operands[2];
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" }
[(set_attr "type" "sseiadd") else
(set_attr "prefix_extra" "1") {
(set_attr "prefix" "vex") xops[1] = operands[2];
(set_attr "mode" "OI")]) xops[2] = operands[1];
}
code = (<CODE> == UMAX || <CODE> == UMIN) ? GTU : GT;
xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
gcc_assert (ok);
DONE;
})
(define_expand "<code><mode>3"
[(set (match_operand:VI124_128 0 "register_operand" "")
(smaxmin:VI124_128 (match_operand:VI124_128 1 "register_operand" "")
(match_operand:VI124_128 2 "register_operand" "")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1 || <MODE>mode == V8HImode)
ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
else
{
rtx xops[6];
bool ok;
xops[0] = operands[0];
if (<CODE> == SMAX)
{
xops[1] = operands[1];
xops[2] = operands[2];
}
else
{
xops[1] = operands[2];
xops[2] = operands[1];
}
xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
gcc_assert (ok);
DONE;
}
})
(define_insn "*sse4_1_<code><mode>3" (define_insn "*sse4_1_<code><mode>3"
[(set (match_operand:VI14_128 0 "register_operand" "=x,x") [(set (match_operand:VI14_128 0 "register_operand" "=x,x")
...@@ -5903,58 +5954,50 @@ ...@@ -5903,58 +5954,50 @@
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_expand "<code><mode>3" (define_expand "<code><mode>3"
[(set (match_operand:VI14_128 0 "register_operand" "") [(set (match_operand:VI124_128 0 "register_operand" "")
(smaxmin:VI14_128 (match_operand:VI14_128 1 "register_operand" "") (umaxmin:VI124_128 (match_operand:VI124_128 1 "register_operand" "")
(match_operand:VI14_128 2 "register_operand" "")))] (match_operand:VI124_128 2 "register_operand" "")))]
"TARGET_SSE2" "TARGET_SSE2"
{ {
if (TARGET_SSE4_1) if (TARGET_SSE4_1 || <MODE>mode == V16QImode)
ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands); ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
else if (<CODE> == UMAX && <MODE>mode == V8HImode)
{
rtx op0 = operands[0], op2 = operands[2], op3 = op0;
if (rtx_equal_p (op3, op2))
op3 = gen_reg_rtx (V8HImode);
emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2));
emit_insn (gen_addv8hi3 (op0, op3, op2));
DONE;
}
else else
{ {
rtx xops[6]; rtx xops[6];
bool ok; bool ok;
xops[0] = operands[0]; xops[0] = operands[0];
xops[1] = operands[<CODE> == SMAX ? 1 : 2];
xops[2] = operands[<CODE> == SMAX ? 2 : 1]; if (<CODE> == UMAX)
xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]); {
xops[1] = operands[1];
xops[2] = operands[2];
}
else
{
xops[1] = operands[2];
xops[2] = operands[1];
}
xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
xops[4] = operands[1]; xops[4] = operands[1];
xops[5] = operands[2]; xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops); ok = ix86_expand_int_vcond (xops);
gcc_assert (ok); gcc_assert (ok);
DONE; DONE;
} }
}) })
(define_expand "<code>v8hi3"
[(set (match_operand:V8HI 0 "register_operand" "")
(smaxmin:V8HI
(match_operand:V8HI 1 "nonimmediate_operand" "")
(match_operand:V8HI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, V8HImode, operands);")
(define_expand "<code><mode>3"
[(set (match_operand:VI8_AVX2 0 "register_operand" "")
(smaxmin:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "")
(match_operand:VI8_AVX2 2 "register_operand" "")))]
"TARGET_SSE4_2"
{
rtx xops[6];
bool ok;
xops[0] = operands[0];
xops[1] = operands[<CODE> == SMAX ? 1 : 2];
xops[2] = operands[<CODE> == SMAX ? 2 : 1];
xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
gcc_assert (ok);
DONE;
})
(define_insn "*sse4_1_<code><mode>3" (define_insn "*sse4_1_<code><mode>3"
[(set (match_operand:VI24_128 0 "register_operand" "=x,x") [(set (match_operand:VI24_128 0 "register_operand" "=x,x")
(umaxmin:VI24_128 (umaxmin:VI24_128
...@@ -5986,103 +6029,6 @@ ...@@ -5986,103 +6029,6 @@
(set_attr "prefix" "orig,vex") (set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_expand "<code>v16qi3"
[(set (match_operand:V16QI 0 "register_operand" "")
(umaxmin:V16QI
(match_operand:V16QI 1 "nonimmediate_operand" "")
(match_operand:V16QI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, V16QImode, operands);")
(define_expand "umaxv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "")
(umax:V8HI (match_operand:V8HI 1 "register_operand" "")
(match_operand:V8HI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1)
ix86_fixup_binary_operands_no_copy (UMAX, V8HImode, operands);
else
{
rtx op0 = operands[0], op2 = operands[2], op3 = op0;
if (rtx_equal_p (op3, op2))
op3 = gen_reg_rtx (V8HImode);
emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2));
emit_insn (gen_addv8hi3 (op0, op3, op2));
DONE;
}
})
(define_expand "umaxv4si3"
[(set (match_operand:V4SI 0 "register_operand" "")
(umax:V4SI (match_operand:V4SI 1 "register_operand" "")
(match_operand:V4SI 2 "register_operand" "")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1)
ix86_fixup_binary_operands_no_copy (UMAX, V4SImode, operands);
else
{
rtx xops[6];
bool ok;
xops[0] = operands[0];
xops[1] = operands[1];
xops[2] = operands[2];
xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
gcc_assert (ok);
DONE;
}
})
(define_expand "umin<mode>3"
[(set (match_operand:VI24_128 0 "register_operand" "")
(umin:VI24_128 (match_operand:VI24_128 1 "register_operand" "")
(match_operand:VI24_128 2 "register_operand" "")))]
"TARGET_SSE2"
{
if (TARGET_SSE4_1)
ix86_fixup_binary_operands_no_copy (UMIN, <MODE>mode, operands);
else
{
rtx xops[6];
bool ok;
xops[0] = operands[0];
xops[1] = operands[2];
xops[2] = operands[1];
xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
gcc_assert (ok);
DONE;
}
})
(define_expand "<code><mode>3"
[(set (match_operand:VI8_AVX2 0 "register_operand" "")
(umaxmin:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "")
(match_operand:VI8_AVX2 2 "register_operand" "")))]
"TARGET_SSE4_2"
{
rtx xops[6];
bool ok;
xops[0] = operands[0];
xops[1] = operands[<CODE> == UMAX ? 1 : 2];
xops[2] = operands[<CODE> == UMAX ? 2 : 1];
xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
gcc_assert (ok);
DONE;
})
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;
;; Parallel integral comparisons ;; Parallel integral comparisons
......
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