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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
51f53e01
Commit
51f53e01
authored
Sep 14, 1999
by
Jeff Law
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Fix typo in comment.
From-SVN: r29392
parent
66519c70
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gcc/loop.c
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51f53e01
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@@ -4053,7 +4053,7 @@ strength_reduce (scan_start, end, loop_top, insn_count,
/* The register from BL2 must be set before the register from
BL is set, or we must be able to move the latter set after
the former set. Currently there can't be any labels
in-between when biv_toal_increment returns nonzero both times
in-between when biv_to
t
al_increment returns nonzero both times
but we test it here in case some day some real cfg analysis
gets used to set always_computable. */
&&
((
loop_insn_first_p
(
bl2
->
biv
->
insn
,
bl
->
biv
->
insn
)
...
...
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