Change (reg:CC 17) to (reg:SI 17)

From-SVN: r22221

gcc/ChangeLog

+Tue Sep  1 11:30:33 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* config/m32r/m32r.md: Change (reg:CC 17) to (reg:SI 17).
+	* config/m32r/m32r.h: Make register 17 be fixed.
+	* config/m32r/m32r.c: Use SImode for cc operations.
+
 Thu Sep  3 18:17:34 1998 Benjamin Kosnik  <bkoz@cygnus.com>
 
 	* invoke.texi (Warning Options): Add -Wnon-template-friend

gcc/config/m32r/m32r.c

@@ -898,7 +898,7 @@ m32r_select_cc_mode (op, x, y)
      int op;
      rtx x, y;
 {
-  return (int)CCmode;
+  return (int)SImode;
 }
 
 /* X and Y are two things to compare using CODE.  Emit the compare insn and
@@ -2150,7 +2150,7 @@ carry_compare_operand (op, int_mode)
 {
   rtx x;
 
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
+  if (GET_MODE (op) != SImode && GET_MODE (op) != VOIDmode)
     return FALSE;
 
   if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
@@ -2179,7 +2179,8 @@ emit_cond_move (operands, insn)
      rtx   insn;
 {
   static char buffer [100];
-
+  char * dest = reg_names [REGNO (operands [0])];
+  
   buffer [0] = 0;
   
   /* Destination must be a register.  */
@@ -2190,7 +2191,6 @@ emit_cond_move (operands, insn)
   if (! conditional_move_operand (operands [3], SImode))
     abort();
       
-
   /* Check to see if the test is reversed.  */
   if (GET_CODE (operands [1]) == NE)
     {
@@ -2199,24 +2199,13 @@ emit_cond_move (operands, insn)
       operands [3] = tmp;
     }
 
-  /* Catch a special case where 0 or 1 is being loaded into the destination.
-     Since we already have these values in the C bit we can use a special
-     instruction.  */
-  if (zero_and_one (operands [2], operands [3]))
-    {
-      char * dest = reg_names [REGNO (operands [0])];
-      
-      sprintf (buffer, "mvfc %s, cbr", dest);
-
-      /* If the true value was '0' then we need to invert the results of the move.  */
-      if (INTVAL (operands [2]) == 0)
-	sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
-		 dest, dest);
-      
-      return buffer;
-    }
-
-
+  sprintf (buffer, "mvfc %s, cbr", dest);
+  
+  /* If the true value was '0' then we need to invert the results of the move.  */
+  if (INTVAL (operands [2]) == 0)
+    sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
+	     dest, dest);
+  
   return buffer;
 }
 

gcc/config/m32r/m32r.h

@@ -434,7 +434,7 @@ if (GET_MODE_CLASS (MODE) == MODE_INT		\
 #define FIXED_REGISTERS \
 { 0, 0, 0, 0, 0, 0, 0, 0,	\
   0, 0, 0, 0, 0, 0, 0, 1,	\
-  1, 0 }
+  1, 1 }
 
 
 /* 1 for registers not available across function calls.

gcc/config/m32r/m32r.md

@@ -802,7 +802,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI (match_operand:DI 1 "register_operand" "%0")
 		 (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:CC 17))]
+   (clobber (reg:SI 17))]
   ""
   "#"
   [(set_attr "type" "multi")
@@ -839,7 +839,7 @@
 }")
 
 (define_insn "*clear_c"
-  [(set (reg:CC 17)
+  [(set (reg:SI 17)
 	(const_int 0))
    (use (match_operand:SI 0 "register_operand" "r"))]
   ""
@@ -851,8 +851,8 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(plus:SI (match_operand:SI 1 "register_operand" "%0")
 		 (plus:SI (match_operand:SI 2 "register_operand" "r")
-			  (reg:CC 17))))
-   (set (reg:CC 17)
+			  (reg:SI 17))))
+   (set (reg:SI 17)
 	(unspec [(const_int 0)] 3))]
   ""
   "addx %0,%2"
@@ -872,7 +872,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(minus:DI (match_operand:DI 1 "register_operand" "0")
 		  (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:CC 17))]
+   (clobber (reg:SI 17))]
   ""
   "#"
   [(set_attr "type" "multi")
@@ -912,8 +912,8 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (match_operand:SI 1 "register_operand" "%0")
 		  (minus:SI (match_operand:SI 2 "register_operand" "r")
-			    (reg:CC 17))))
-   (set (reg:CC 17)
+			    (reg:SI 17))))
+   (set (reg:SI 17)
 	(unspec [(const_int 0)] 3))]
   ""
   "subx %0,%2"
@@ -1080,8 +1080,8 @@
 ;; preferred.
 
 (define_expand "cmpsi"
-  [(set (reg:CC 17)
-	(compare:CC (match_operand:SI 0 "register_operand" "")
+  [(set (reg:SI 17)
+	(compare:SI (match_operand:SI 0 "register_operand" "")
 		    (match_operand:SI 1 "nonmemory_operand" "")))]
   ""
   "
@@ -1097,8 +1097,8 @@
 ;; is quite inefficient.  However, it is rarely used.
 
 (define_insn "cmp_eqsi_insn"
-  [(set (reg:CC 17)
-	(eq:CC (match_operand:SI 0 "register_operand" "r,r")
+  [(set (reg:SI 17)
+	(eq:SI (match_operand:SI 0 "register_operand" "r,r")
 	       (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
    (clobber (match_scratch:SI 2 "=&r,&r"))]
   ""
@@ -1122,8 +1122,8 @@
    (set_attr "length" "8,8")])
 
 (define_insn "cmp_ltsi_insn"
-  [(set (reg:CC 17)
-	(lt:CC (match_operand:SI 0 "register_operand" "r,r")
+  [(set (reg:SI 17)
+	(lt:SI (match_operand:SI 0 "register_operand" "r,r")
 	       (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
   ""
   "@
@@ -1133,8 +1133,8 @@
    (set_attr "length" "2,4")])
 
 (define_insn "cmp_ltusi_insn"
-  [(set (reg:CC 17)
-	(ltu:CC (match_operand:SI 0 "register_operand" "r,r")
+  [(set (reg:SI 17)
+	(ltu:SI (match_operand:SI 0 "register_operand" "r,r")
 	        (match_operand:SI 1 "reg_or_uint16_operand" "r,K")))]
   ""
   "@
@@ -1691,7 +1691,14 @@
   ]
 )
 
-
+(define_insn "movcc_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(reg:SI 17))]
+  ""
+  "mvfc %0, cbr"
+  [(set_attr "type" "misc")
+   (set_attr "length" "2")]
+)
 
 
 ;; Split up troublesome insns for better scheduling.